NEC V854 UPD703006 User Manual page 270

32/16-bit single-chip microcontroller hardware
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(8) Interrupt request (INTIIC) generation timing and wait control
INTIIC generates and wait control is performed by the settings of the WTIM bit of the IIC control register (IICC)
at the timings shown in Table 8-3.
WTIM
Address
0
9
Notes 1, 2
1
9
Notes 1, 2
Notes 1. INTIIC signal and wait of the slave generate at the fall of the ninth clock only when they coincide with
the address set in the slave address register (SVA).
At this time, ACK is output regardless of the setting of ACKE. The slave which has received an extension
code generates INTIIC at the fall of the eighth clock.
2. Neither INTIIC nor wait generates when SVA and the received address do not coincide.
Remark The numbers in the table represent the number of the clocks of the serial clock. Both the interrupt request
and the wait control synchronize with the fall of the serial clock.
(a) When transmitting/receiving address
• In slave operation
• In master operation : The interrupt and the wait timings generates at the fall of the ninth clock
(b) When receiving data
• In master/slave operation: The interrupt and the wait timings are determined by the WTIM bit.
(c) When transmitting data
• In master/slave operation: The interrupt and the wait timings are determined by the WTIM bit.
(d) Wait release
The following four methods are available for releasing wait.
• Set WREL of the control register (IICC) = 1
• Write operation of IIC shift register (IIC)
• Start condition (STT) set
• Stop condition (SPT) set
When 8-clock wait (WTIM = 0) is selected, the output level of ACK should be determined before wait
release.
(e) Stop condition detection
INTIIC generates when stop condition is detected.
270
CHAPTER 8 SERIAL INTERFACE FUNCTION
Table 8-3. INTIIC Generation Timing and Wait Control
In Slave Operation
Data Reception Data Transmission
8
Note 2
8
Note 2
9
Note 2
9
Note 2
: The interrupt and the wait timings are determined regardless of the WTIM bit.
regardless of the WTIM bit.
User's Manual U11969EJ3V0UM00
In Master Operation
Address
Data Reception Data Transmission
9
8
9
9
8
9

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