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(1) Clock output mode register (CLOM)
This register controls clock output function. This register can be read/written in 8- or 1-bit units.
7
6
CLOM
LV
0
Bit Position
Bit Name
7
LV
4
CLE
2 to 0
FS2 to
FS0
Caution Do not change the values of the other bits (LV, FS2 to FS0) during setting of the CLE bit (1).
Do not change the values of other bits (LV, FS2 to FS0) simultaneously with changing the
value of the CLE bit.
(2) 1-bit output port
When the CLE bit is 0, CLO pin outputs the signals of the same level as that of the LV bit. When the contents
of the LV bit is changed, CLO signal changes immediately.
LV
CLO
154
CHAPTER 6 CLOCK GENERATOR FUNCTION
5
4
3
0
CLE
0
Level
Selects output level of CLO signal
0 : Low-level output
1 : High-level output
Clock Enable
Controls clock output of CLO signal
0 : Outputs the contents of LV bit
1 : Outputs the clock selected by FS2 to FS0 bits
Frequency Select
Selects the frequency of CLO signal
FS2
FS1
FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Others
φ : Internal system clock
Remark
LV ← 1
User's Manual U11969EJ3V0UM00
2
1
0
FS2
FS1
FS0
FFFFF3D0H
Function
Selection of Frequency
φ
φ /2
φ /4
φ /8
φ /16
Setting prohibited
LV ← 0
Address
After reset
00H
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