Table of Contents
Advertisement
(2) IIC status register (IICS)
IIC status register indicates the I
This register is set by 1- or 8-bit memory manipulation instruction. It can only be read.
It becomes 00H by RESET input.
7
6
IICS
MSTS
ALD
Bit Position
Bit Name
7
MSTS
6
ALD
5
EXC
4
COI
CHAPTER 8 SERIAL INTERFACE FUNCTION
2
C status.
5
4
3
EXC
COI
TRC
Master Status
Indicates master status.
0 : Slave status or communication wait status
1 : Master status
Set condition
: Start condition generation
Clear condition : Stop condition detection, ALD = 1, LREL = 1, IICE = 1 -> 0, or reset input
Arbitration Defeat
Detects arbitration defeat.
0 : Arbitration has not occurred, or win in arbitration
1 : Defeat in arbitration. MSTS flag is cleared.
Set condition
: Arbitration defeat
Clear condition : IICE = 0, reset input, or after IICS read.
A bit manipulation instruction is executed to another bit of the IICS register.
Extension Code
Indicates reception of extension code.
0 : Extension code is not received
1 : Extension code is received
Set condition
: The higher 4 bits of the received address are 0000 or 1111 (set at the rise of
the eighth clock).
Clear condition : Start condition detection, stop condition detection, LREL= 1, IICE = 0, or reset
input
Coincident Address
Indicates coincidence of received address and local address.
0 : Addresses do not coincide
1 : Addresses coincide
Set condition
: Coincidence of received address and local address (SVA) (set at the rise of
the eighth clock)
Clear condition : Start condition detection, LREL = 1, IICE = 0, or reset input
User's Manual U11969EJ3V0UM00
2
1
0
ACKD
STD
SPD
Function
Address
After reset
FFFFF0E2H
00H
239
Advertisement
Table of Contents
