NEC V854 UPD703006 User Manual page 238

Bit Position Bit Name
3 WTIM
2 ACKE
1 STT
0 SPT
Caution When performing transmission/reception of master between enabling operation (IICE = 1) and
the first stop condition detection, generate a stop condition once by setting the SPT bit.
238
CHAPTER 8 SERIAL INTERFACE FUNCTION
Wait Timing
Controls generation of wait and interrupt request.
0 : Interrupt request generates at the fall of the eighth clock
For master : Waits keeping clock output in low level after outputting eight clocks
For slave : Waits for master setting clock output in low level after inputting eight clocks
1 : Interrupt request generates at the fall of the ninth clock
For master : Waits keeping clock output in low level after outputting nine clocks
For slave : Waits for master setting clock output in low level after inputting nine clocks
The setting of this bit becomes invalid while transferring address. When EXC = 1, wait is
compulsorily inserted at the eighth clock, and when COI = 1, wait is compulsorily inserted at the
ninth clock, and then the setting of this bit becomes valid. For master, wait is inserted at the ninth
clock while transferring address. The slave which has received the local address enters wait
status at the fall of the ninth clock after the generation of acknowledge.
Set condition : Instruction
Clear condition : Instruction, reset input
Acknowledge Enable
Controls acknowledge.
0 : Disables acknowledge
1 : Enables automatic acknowledge output. SDA line becomes low level during the 9-clock
period. However, it is invalid while transferring address and valid when EXC = 1.
Set condition : Instruction
Clear condition : Instruction, reset input
Start Condition Trigger
Selects whether generating start condition or not.
0 : Does not generate start condition
1 : Generates start condition
When bus is released (stop status): generates start condition by changing SDA line from
high-level to low-level (starts up as master). And then, secures specification time and sets
SCL to low level.
When not joining bus (STT is set after STD =1 is set): this bit functions as a start condition
reservation flag. When this bit is set, it automatically generates start condition after bus is
released.
Set condition : Instruction
Clear condition : Instruction, reset input, when start condition is detected for master, (MSTS =
1 and STD = 1), or when defeated in arbitration.
Stop Condition Trigger
Selects whether generating stop condition or not.
If this bit is set in the early stage of communication, it outputs low-level to SDA line and generates
stop condition.
0 : Does not generate stop condition
1 : Generates stop condition
Sets SCL line to high level after setting SDA line to low level, or waits SCL becomes high
level. And then, it secures specification time , changes SDA line from low level to high level,
and generates stop condition.
Set condition : Instruction
Clear condition : Instruction, reset input, when stop condition is detected, or when defeated in
arbitration.
User's Manual U11969EJ3V0UM00
Function