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Bit Position
Bit Name
3
TRC
2
ACKD
1
STD
0
SPD
240
CHAPTER 8 SERIAL INTERFACE FUNCTION
Transmit/Receive Condition
Indicates current communication status.
0 : Receiving status (status other than transmitting status). SDA line goes into high-impedance
state.
1 : Transmitting status. The value of SO latch can be output to SDA line (valid after the fall of
the ninth clock of the first byte).
Set condition
: Start condition generation (STD = 1 and MSTS = 1) for master.
1 is input to the LSB (transfer direction specification bit) of the first byte for
slave.
Clear condition : LREL = 1, IICE = 0, ALD = 1, reset input, stop condition detection.
1 is output to the LSB (transfer direction specification bit) of the first byte for
master.
Start condition detection (STD = 1 and MSTS = 0) for slave when not joining
communication.
Acknowledge Detected
Indicates detection of acknowledge signal.
0 : Not detected
1 : Detected
Set condition
: SDA line becomes low-level at the rise of the ninth clock of SCL.
Clear condition : LREL = 1, the rise of the first clock of the next byte, stop condition detection,
IICE= 0, or reset input
Start Condition Detected
Indicates detection of start condition.
0 : Start condition not detected
1 : Start condition detected. Indicates address transfer period.
Set condition
: Start condition detection
Clear condition : Stop condition detection, LREL = 1, the rise of the first clock of the byte following
the address transfer period, IICE = 0, or reset input
Stop Condition Detected
Indicates detection of stop condition.
0 : Stop condition not detected
1 : Stop condition detected. Communication in the master ends. Bus is released.
Set condition
: Stop condition detection
Clear condition : The rise of the first clock of the address transfer byte after start condition
detection and after setting this bit, IICE = 0, or reset input.
Cleared with clock input even without start condition.
User's Manual U11969EJ3V0UM00
Function
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