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(6) Wait signal (WAIT)
The wait signal is a signal by which the master or the slave informs the other that it is preparing for transmitting/
receiving data (wait status).
The master of the slave informs the wait status to the other by inputting the low level to the SCL pin. Both
the master and slave can start the next transfer when the wait status is released.
(1) When the master is 9-clock wait, and the slave is 8-clock wait
(master: transmission, slave: reception, ACKE = 1)
Master
IIC
6
SCL
Slave
IIC
SCL
ACKE
H
Transfer line
6
SCL
SDA
D2
248
CHAPTER 8 SERIAL INTERFACE FUNCTION
Figure 8-20. Wait Signal (1/2)
Slave is waiting (low level)
while master returns to Hi-Z
7
8
9
Waits after outputting
the eighth clock
7
8
D1
D0
ACK
User's Manual U11969EJ3V0UM00
Waits after outputting
the ninth clock
IIC ← data (wait released)
1
IIC ← FFH (wait released) or WREL ← 1
9
1
D7
2
3
2
3
D6
D5
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