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6.5.5 Software STOP mode
(1) Entering and operation status
In this mode, the CPU clock, the internal system clock, and the clock generator are stopped, reducing power
consumption to only leakage current. In this state, power consumption is minimized.
The software STOP mode is entered by programming the PSC register (Specific register) using the store (ST/
SST) or bit manipulation (SET1/CLR1/NOT1) instruction (refer to 3.4.9 Specific register).
It is necessary to ensure the oscillation stabilization time of the oscillator circuit after the software STOP mode
has been released, when the oscillator connection mode (CESEL bit = "0") are set.
In the software STOP mode, program execution is stopped, but all the contents of the registers and internal
RAM immediately before entering the STOP mode are retained. The on-chip peripheral function also stops
operation.
Table 6-4 shows the hardware status in the software STOP mode.
Function
Clock Generator
Internal System Clock
CPU
I/O Port
Note 1
Peripheral Function
Internal Data
External
Expansion
Mode
CLKOUT
CLO
Notes 1. When the value of V
Even if V
of the internal RAM can be retained if the data retention voltage V
is maintained.
2. Set the CLE bit of the CLOM register to 0 before switching over to the
software STOP mode.
CHAPTER 6 CLOCK GENERATOR FUNCTION
Table 6-4. Operating Status in Software STOP Mode
Stops
Stops
Stops
Retained
Stops
Note 1
Status of all internal data immediately before software
STOP mode is set, such as CPU registers, status, data,
and internal RAM contents, are retained.
AD0 to AD15
High-impedance
A16 to A23
LBEN, UBEN
R/W
DSTB, WRL,
WRH, RD
ASTB
HLDAK
Low level output
Retained
Note 2
is within the operating range.
DD
drops below the minimum operating voltage, the contents
DD
User's Manual U11969EJ3V0UM00
Operating Status
DDDR
147
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