NEC V854 UPD703006 User Manual page 138

The sequence of setting data in this register is the same as the power save control register (PSC). However, the
limitation items listed in Cautions 2 for the 3.4.9 Specific registers do not apply. For details, refer to 6.5.2 Control
register.
(1) Example of settings
The example of settings is as below.
Operation Mode
CKSEL
Direct mode
PLL mode (1-x
multiplication)
PLL mode (5-x
multiplication)
Other than the above
Note Connect directly to V
Remark H : High level input
L : Low level input
138
CHAPTER 6 CLOCK GENERATOR FUNCTION
Pins CKC Register
PLLSEL CKDIV1
H Note 0
L L 0
L L 1
L L 1
L H 0
L H 1
L H 1
or V .
DD SS
User's Manual U11969EJ3V0UM00
Input Clock
(f )
XX
CKDIV0
0 16 MHz
0 33 MHz
0 33 MHz
1 33 MHz
0 6.6 MHz
0 6.6 MHz
1 6.6 MHz
Setting prohibited
Internal System
Clock ( φ )
8 MHz
33 MHz
6.6 MHz
3.3 MHz
33 MHz
6.6 MHz
3.3 MHz