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CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
7.2.1 Timer 0
(1) Timers 0, 0L (TM0, TM0L)
TM0 functions as a 24-bit interval timer, free-running timer or event counter for external signals. It is used
to measure cycles and frequency, and also for pulse generation.
Only 32-bit read access is enabled for TM0 (however, the high-order 8 bits are fixed to 0), and only 16-bit read
access is enabled for TM0L.
To read the low-order 24 bits of timer 0, specify TM0 with word access, and to read the low-order 16 bits only,
specify TM0 with half-word access.
31
24 23
TM0
00000000
TM0 counts up the internal count clock or external count clock. The timer is started or stopped by the CE0
bit of timer control register 00 (TMC00).
(2) Capture/compare registers 00 to 03 (CC00 to CC03, CC00L to CC03L)
The capture/compare registers are 24-bit registers connected to TM0. They can be used as capture registers
or compare registers depending on the specification of timer control register 01 (TMC01).
32-bit read/write access is enabled for CC0n (however, the high-order 8 bits are fixed to 0, and are ignored
during write operation), and 16-bit read/write access is enabled for CC0nL.
To access the low-order 24 bits or the low-order 16 bits of these registers, specify CC0n and CC0nL,
respectively.
31
24 23
CC0n
00000000
Remark n = 0 to 3
(a) When used as a capture register
When a capture/compare register is used as a capture register, it detects the valid edge of the
corresponding external interrupt INTPn (n = 10 to 13) as a capture trigger. Timer 0 latches the count value
in synchronization with the capture trigger (capture operation). The latched value is held by the capture
register until the next capture operation is performed.
(b) When used as a compare register
When a capture/compare register is used as a compare register, it compares its contents with the value
of the timer at each clock tick.
Compare registers support the set/reset output function. In other words, they set or reset the corresponding
timer output synchronously with the coincidence signal generation.
15
TM0L
15
CC0nL
User's Manual U11969EJ3V0UM00
0
Address
After reset
FFFFF250H
00000000H
0
Address
At reset
FFFFF264H
0000H
0
Addresses
After reset
FFFFF254H to
Undefined
FFFFF260H
0
Addresses
After reset
FFFFF266H to
Undefined
FFFFF26CH
161
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