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(2) When both master and slave are 9-clock wait
(master: transmission, slave: reception, ACKE = 1)
Master
IIC
6
SCL
Slave
IIC
SCL
ACKE
H
Transfer line
6
SCL
SDA
D2
D1
The wait of the IICC register automatically generates according to the setting of WTIM.
Normally, the receive side releases wait when WREL = 1 or when FFH is written to IIC, and the transmit side
releases wait when data is written to IIC.
For the master, wait can be released also with the following method.
• STT = 1
• SPT = 1
CHAPTER 8 SERIAL INTERFACE FUNCTION
Figure 8-20. Wait Signal (2/2)
Both master and slave wait
after outputting the ninth clock
7
8
9
7
8
9
D0
ACK
Output according to the ACKE previously set.
User's Manual U11969EJ3V0UM00
IIC ← data (wait released)
1
2
IIC ← FFH (wait released)
or WREL ← 1
1
2
D7
D6
3
3
D5
249
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