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8.4.8 Timing chart
In the I
2
C bus mode, a target slave device is selected from more than one slave device when the master outputs
an address to the serial bus.
The master transmits the TRC bit that indicates the transfer direction of data following the slave address and starts
serial communication with the slave.
Figures 8-27 and 8-28 show the timing charts of data communication.
The shift operation of the shift register (IIC) is performed in synchronization with the fall of the serial clock (SCK),
the transmitted data is transferred to the SO latch, and output from the SDA pin with the MSB first.
The data input to the SDA pin at the rise of SCL is captured by IIC.
CHAPTER 8 SERIAL INTERFACE FUNCTION
User's Manual U11969EJ3V0UM00
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