Operations In Halt And Sleep Modes; Control Registers; Wdt2 Clock Control Register - Epson S1C17W12 Technical Manual

8.3.2 Operations in HALT and SLEEP Modes

During HALT mode
WDT2 operates in HALT mode. HALT mode is therefore cleared by an NMI or reset if it continues for more than the
NMI/reset generation cycle and the CPU executes the interrupt handler. To disable WDT2 in HALT mode, stop WDT2
by writing 0xa to the WDTCTL.WDTRUN[3:0] bits before executing the halt instruction. Reset WDT2 before re-
suming operations after HALT mode is cleared.
During SLEEP mode
WDT2 operates in SLEEP mode if the selected clock source is running. SLEEP mode is cleared by an NMI or reset if
it continues for more than the NMI/reset generation cycle and the CPU executes the interrupt handler. Therefore, stop
WDT2 by setting the WDTCTL.WDTRUN[3:0] bits before executing the slp instruction.
If the clock source stops in SLEEP mode, WDT2 stops. To prevent generation of an unnecessary NMI or reset after
clearing SLEEP mode, reset WDT2 before executing the slp instruction. WDT2 should also be stopped as required us-
ing the WDTCTL.WDTRUN[3:0] bits.

8.4 Control Registers

WDT2 Clock Control Register

Register name Bit
WDTCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the WDT2 operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the WDT2 operating clock (counter clock). The clock frequency
should be set to around 256 Hz.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of WDT2.
WDTCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
S1C17W12/W13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x0
Table 8.4.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/16,384
1/8,192
1/4,096
1/2,048
Seiko Epson Corporation
Reset R/W
– R –
H0 R/WP
– R
H0 R/WP
– R
H0 R/WP
WDTCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/128 1/16,384
1/8,192
1/4,096
1/2,048
8 WATCHDOG TIMER (WDT2)
Remarks
0x3
EXOSC
1/1
8-3