8-Bit Timer/Counter Register Description - Atmel ATtiny25 Manual

12.8

8-bit Timer/Counter Register Description

12.8.1 Timer/Counter Control Register A – TCCR0A
ATtiny25/45/85
72
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f
clk_I/O
clk
I/O
clk
Tn
(clk /8)
I/O
TCNTn
(CTC)
OCRnx
OCFnx
Bit 7
COM0A1 COM0A0
Read/Write R/W
Initial Value 0
• Bits 7:6 – COM01A:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 12-1
are set to a normal or CTC mode (non-PWM).
Table 12-1. Compare Output Mode, non-PWM Mode
COM01 COM00
0 0
0 1
1 0
1 1
Table 12-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 12-2. Compare Output Mode, Fast PWM Mode
COM01 COM00
0 0
/8)
TOP - 1 TOP
6 5 4
COM0B1 COM0B0
R/W R/W R/W
0 0 0
shows the COM0A1:0 bit functionality when the WGM02:0 bits
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A on Compare Match
Description
Normal port operation, OC0A disconnected.
BOTTOM
TOP
3 2 1
– – WGM01
R R R/W
0 0 0
(1)
BOTTOM + 1
0
WGM00 TCCR0A
R/W
0
7598H–AVR–07/09