Atmel ATtiny25 Manual
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Atmel ATtiny25 Manual

Microcontroller with 2/4/8k bytes in-system programmable flash
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Features

•
High Performance, Low Power AVR
•
Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
•
Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
•
Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
•
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
•
I/O and Packages
– Six Programmable I/O Lines
– 8-pin SOIC
– 20-pin QFN
•
Operating Voltage
– 2.7 - 5.5V for ATtiny25/45/85
•
Speed Grade
– ATtiny25/45/85: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
•
Automotive Temperature Range
– -40°C to +125°C
•
Low Power Consumption
– Active Mode:
• 1 MHz, 2.7V: 300µA
– Power-down Mode:
• 0.2µA at 2.7V
®
8-Bit Microcontroller
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25
ATtiny45
ATtiny85
Automotive
7598H–AVR–07/09

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Summary of Contents for Atmel ATtiny25

  • Page 1: Features

    • Operating Voltage – 2.7 - 5.5V for ATtiny25/45/85 • Speed Grade – ATtiny25/45/85: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V • Automotive Temperature Range – -40°C to +125°C • Low Power Consumption –...

  • Page 2: Pin Configurations

    PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

  • Page 3: Block Diagram

    ATtiny25/45/85 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS CALIBRATED INTERNAL OSCILLATOR PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL REGISTER PROGRAM SRAM FLASH MCU STATUS REGISTER GENERAL INSTRUCTION REGISTER PURPOSE REGISTERS TIMER/ COUNTER0 INSTRUCTION DECODER TIMER/...

  • Page 4: Automotive Quality Grade

    On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

  • Page 5: Pin Descriptions

    The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on page 2.3.4 RESET Reset input.

  • Page 6: Architectural Overview

    Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 7: Alu - Arithmetic Logic Unit

    ATtiny25/45/85 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation.
  • Page 8 The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 9: General Purpose Register File

    ATtiny25/45/85 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input •...

  • Page 10: Stack Pointer

    Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. SP15 SP14 SP13 SP12 SP11 SP10 Read/Write Initial Value ATtiny25/45/85 7598H–AVR–07/09...

  • Page 11: Instruction Execution Timing

    ATtiny25/45/85 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk , directly generated from the selected clock source for the chip. No internal clock division is used.
  • Page 12 = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATtiny25/45/85 7598H–AVR–07/09...

  • Page 13: Avr Attiny25/45/85 Memories

    This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are lin- ear and regular.

  • Page 14: Sram Data Memory

    X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File”...

  • Page 15: Eeprom Data Memory

    Next Instruction EEPROM Data Memory The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
  • Page 16 • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
  • Page 17 ATtiny25/45/85 • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny25/45/85 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE.
  • Page 18 The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions ATtiny25/45/85 7598H–AVR–07/09...
  • Page 19 ATtiny25/45/85 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; Set up address (r17) in address register out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ;...
  • Page 20 BOD does not match the needed detection level, an external low V reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 21: I/O Memory

    “Register Summary” on page 182. All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
  • Page 22 Internal PLL for Fast Peripheral Clock Generation - clk The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. The source of the PLL input clock is the output of the internal RC oscillator having a frequency of 8.0 MHz.

  • Page 23: Clock Sources

    ATtiny25/45/85 Figure 6-2. PCK Clocking System OSCCAL PLLCK & CKSEL FUSES PLLE CLKPS3..0 PLOCK Lock Detector RC OSCILLATOR 8x / 4x 8.0 MHz / 6.4 MHz 64 / 25.6 MHz DIVIDE BY 4 SYSTEM System CLOCK Clock Prescaler XTAL1 OSCILLATORS...

  • Page 24: Default Clock Source

    12 - 22 8.0 - 12 - 22 Notes: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 6-4. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 25: Low-Frequency Crystal Oscillator

    ATtiny25/45/85 Table 6-4. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Additional Delay Power-down and from Reset CKSEL0 SUT1..0 Power-save = 5.0V) Recommended Usage Ceramic resonator, fast 258 CK 14CK + 4 ms rising power Ceramic resonator, slowly...

  • Page 26: Calibrated Internal Rc Oscillator

    The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 8.8 MHz frequency. Other- wise, the EEPROM or Flash write may fail. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 27: External Clock

    ATtiny25/45/85 The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre- quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

  • Page 28: 128 Khz Internal Oscillator

    Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Additional Delay from SUT1..0 Power-down and Power-save Reset Recommended Usage 6 CK 14CK BOD enabled 6 CK 14CK + 4 ms Fast rising power 6 CK 14CK + 64 ms Slowly rising power Reserved ATtiny25/45/85 7598H–AVR–07/09...

  • Page 29: Clock Output Buffer

    6.10 System Clock Prescaler The ATtiny25/45/85 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.
  • Page 30 From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 31: Power Management And Sleep Modes

    MCU wakes up and executes from the Reset Vector. Figure 6-1 on page 21 presents the different clock systems in the ATtiny25/45/85, and their dis- tribution. The figure is helpful in selecting an appropriate sleep mode.

  • Page 32: Idle Mode

    Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 33: Limitations

    Initial Value • Bits 7, 6, 5, 4- Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3- PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

  • Page 34: Minimizing Power Consumption

    If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt- age Reference” on page 40 for details on the start-up time. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 35: System Control And Reset

    “Clock Sources” on page Reset Sources The ATtiny25/45/85 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V •...

  • Page 36: Power-On Reset

    A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V rise. The RESET signal is activated again, without any delay, when V decreases below the detection level. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 37: External Reset

    ATtiny25/45/85 Figure 8-2. MCU Start-up, RESET Tied to V CCRR PORMA X PORMIN RESET TOUT TIME-OUT INTERNAL RESET Figure 8-3. MCU Start-up, RESET Extended Externally RESET TOUT TIME-OUT INTERNAL RESET Table 8-1. Power On Reset Specifications Symbol Parameter Units Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling) VCC Max.

  • Page 38: Brown-Out Detection

    Figure 8-4. External Reset During Operation Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.

  • Page 39: Watchdog Reset

    ATtiny25/45/85 When the BOD is enabled, and V decreases to a value below the trigger level (V Figure BOT- 8-5), the Brown-out Reset is immediately activated. When V increases above the trigger level Figure 8-5), the delay counter starts the MCU after the Time-out period t...

  • Page 40: Mcu Status Register - Mcusr

    See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

  • Page 41: Watchdog Timer

    Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vec- tor. For timing details on the Watchdog Reset, refer to Table 8-7 on page The Wathdog Timer can also be configured to generate an interrupt instead of a reset.
  • Page 42 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 44. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 43 ATtiny25/45/85 In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCU Status Register – MCUSR” on page 40 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above.

  • Page 44: Timed Sequences For Changing The Configuration Of The Watchdog Timer

    1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ- ten to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 45: Interrupts

    WDCE bit cleared. The value written to the WDE bit is irrelevant. 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”...

  • Page 46: O Ports

    If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny25/45/85 is: Address Labels Code...

  • Page 47: Ports As General Digital I/O

    ATtiny25/45/85 Figure 10-1. I/O Pin Equivalent Schematic Logic See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case “x” repre- sents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used.
  • Page 48 (zero). 10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 49 ATtiny25/45/85 10.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept- able, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
  • Page 50 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 51 ATtiny25/45/85 Assembly Code Example ; Define pull-ups and set outputs high ; Define directions for port pins r16,(1<<PB4)|(1<<PB1)|(1<<PB0) r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) PORTB,r16 DDRB,r17 ; Insert nop for synchronization ; Read port pins r16,PINB C Code Example unsigned char i; /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);...

  • Page 52: Alternate Port Functions

    DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE WPx: WRITE PINx DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE I/O CLOCK SLEEP: SLEEP CONTROL DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE ATtiny25/45/85 7598H–AVR–07/09...
  • Page 53 ATtiny25/45/85 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from...
  • Page 54 The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. ADC0: Analog to Digital Converter, Channel 0 PCINT5: Pin Change Interrupt source 5. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 55 ATtiny25/45/85 • Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4 XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin.
  • Page 56 Internal Voltage Reference with external capacitor at the AREF pin. DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. PCINT0: Pin Change Interrupt source 0. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 57 ATtiny25/45/85 Table 10-4 Table 10-5 relate the alternate functions of Port B to the overriding signals shown in Figure 10-5 on page Table 10-4. Overriding Signals for Alternate Functions in PB5..PB3 Signal PB5/RESET/ PB4/ADC2/XTAL2/ PB3/ADC3/XTAL1/ Name ADC0/PCINT5 OC1B/PCINT4 _OC1B/PCINT3 PUOE RSTDISBL •...

  • Page 58: Register Description For I/O-Ports

    Start-up Time, the MCU will still wake up, but no inter- rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described “System Clock and Clock Options” on page ATtiny25/45/85 7598H–AVR–07/09...

  • Page 59: Mcu Control Register - Mcucr

    Initial Value • Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled.

  • Page 60: General Interrupt Flag Register - Gifr

    Initial Value • Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).

  • Page 61: 12 8-Bit Timer/Counter0 With Pwm

    Figure 12-1. For the actual placement of I/O pins, refer to “Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the “8-bit Timer/Counter Register Description”...

  • Page 62: Timer/Counter Clock Sources

    The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 12-2 shows a block diagram of the counter and its surroundings. Figure 12-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count Edge Detector clear TCNTn Control Logic direction ( From Prescaler ) bottom ATtiny25/45/85 7598H–AVR–07/09...

  • Page 63: Output Compare Unit

    ATtiny25/45/85 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clk in the following. Signalize that TCNT0 has reached maximum value.
  • Page 64 All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial- ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 65: Compare Match Output Unit

    ATtiny25/45/85 12.4.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation.

  • Page 66: Modes Of Operation

    (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 67 ATtiny25/45/85 The timing diagram for the CTC mode is shown in Figure 12-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set...
  • Page 68 The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 69 ATtiny25/45/85 Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1).

  • Page 70: Timer/Counter Timing Diagrams

    The figures include information on when Interrupt Flags are set. Figure 12-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 71 ATtiny25/45/85 Figure 12-8. Timer/Counter Timing Diagram, no Prescaling (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 12-9 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk...

  • Page 72: 8-Bit Timer/Counter Register Description

    Set OC0A on Compare Match Table 12-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 12-2. Compare Output Mode, Fast PWM Mode COM01 COM00 Description Normal port operation, OC0A disconnected. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 73 ATtiny25/45/85 Table 12-2. Compare Output Mode, Fast PWM Mode COM01 COM00 Description WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match, set OC0A at TOP Set OC0A on Compare Match, clear OC0A at TOP Note: 1.
  • Page 74 • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting...
  • Page 75 ATtiny25/45/85 Table 12-7. Waveform Generation Mode Bit Description Timer/Counter Mode of Update of TOV Flag (1)(2) Mode WGM2 WGM1 WGM0 Operation OCRx at Set on Normal 0xFF Immediate PWM, Phase 0xFF BOTTOM Correct OCRA Immediate Fast PWM 0xFF Reserved –...
  • Page 76 The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “Timer/Counter Control Register A –...
  • Page 77 Initial Value • Bits 7..4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled.

  • Page 78: Timer/Counter Prescaler

    CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 79: External Clock Source

    ATtiny25/45/85 13.2 External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk ). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro- nized (sampled) signal is then passed through the edge detector.
  • Page 80 Timer/Counter start counting. • Bit 0 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 81: Counter And Compare Units

    ATtiny25/45/85 14. Counter and Compare Units Figure 14-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro- nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
  • Page 82 PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost. The following Figure 14-3 shows the block diagram for Timer/Counter1. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 83 ATtiny25/45/85 Figure 14-3. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE OC1A OC1A OC1B OC1B FLOW IRQ MATCH A IRQ MATCH B IRQ (PB1) (PB0) (PB4) (PB3) DEAD TIME GENERATOR DEAD TIME GENERATOR TIMER INT. MASK TIMER INT. FLAG...
  • Page 84 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 14-2. Timer/Counter1 Prescale Select Synchronous Asynchronous CS13 CS12 CS11 CS10 Clocking Mode Clocking Mode T/C1 stopped T/C1 stopped PCK/2 CK/2 PCK/4 CK/4 PCK/8 CK/8 PCK/16 CK/16 PCK/32 CK/32 ATtiny25/45/85 7598H–AVR–07/09...
  • Page 85 ATtiny25/45/85 Table 14-2. Timer/Counter1 Prescale Select (Continued) Synchronous Asynchronous CS13 CS12 CS11 CS10 Clocking Mode Clocking Mode PCK/64 CK/64 PCK/128 CK/128 PCK/256 CK/256 PCK/512 CK/512 PCK/1024 CK/1024 PCK/2048 CK/2048 PCK/4096 CK/4096 PCK/8192 CK/8192 PCK/16384 CK/16384 The Stop condition provides a Timer Enable/Disable function.
  • Page 86 Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow- ing the compare event. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 87 Initial value • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled.
  • Page 88 Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 14.1.8 Timer/Counter Interrupt Flag Register - TIFR...
  • Page 89 When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. • Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 14.1.9 PLL Control and Status Register - PLLCSR...
  • Page 90 The value is latched into OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 14-5 for an example. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 91 ATtiny25/45/85 Figure 14-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Glitch Unsynchronized OC1x Latch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location.
  • Page 92 160 kHz PCK/2 0010 170 kHz PCK/2 0010 180 kHz PCK/2 0010 190 kHz PCK/2 0010 200 kHz PCK/2 0010 250 kHz 0001 300 kHz 0001 350 kHz 0001 400 kHz 0001 450 kHz 0001 500 kHz 0001 ATtiny25/45/85 7598H–AVR–07/09...

  • Page 93: Dead Time Generator

    ATtiny25/45/85 15. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B).

  • Page 94: Timer/Counter1 Dead Time Prescaler Register 1 - Dtps1

    Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in table 46.. Table 15-1. Division factors of the Dead Time prescaler DTPS11 DTPS10 Prescaler divides the T/C1 clock by 1x (no division) ATtiny25/45/85 7598H–AVR–07/09...

  • Page 95: Timer/Counter1 Dead Time A - Dt1A

    ATtiny25/45/85 15.2 Timer/Counter1 Dead Time A - DT1A $25 ($45) DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 DT1A Read/Write Initial value The dead time value register A is an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output.

  • Page 96: Universal Serial Interface - Usi

    A simplified block diagram of the USI is shown on Figure 16-1. For the actual placement of I/O pins, refer to “Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “USI Register Descriptions”...

  • Page 97: Functional Descriptions

    ATtiny25/45/85 This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits.
  • Page 98 Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 16.2.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: USIDR,r16 r16,(1<<USIOIF) USISR,r16 r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) SPITransfer_loop: USICR,r16 r16, USISR sbrs r16, USIOIF ATtiny25/45/85 7598H–AVR–07/09...
  • Page 99 ATtiny25/45/85 rjmp SPITransfer_loop r16,USIDR The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is com- pleted the data received from the Slave is stored back into the r16 Register.
  • Page 100 16.2.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim- iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 101 ATtiny25/45/85 Figure 16-4. Two-wire Mode Operation, Simplified Diagram Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HOLD Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PORTxn MASTER Figure 16-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave.
  • Page 102 SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribution” on page 21) must also be taken into the consideration. Refer to the USISIF bit description on page 104 for further details. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 103: Alternative Usi Usage

    ATtiny25/45/85 16.3 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 16.3.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only.
  • Page 104 Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration. • Bits 3..0 – USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 105 ATtiny25/45/85 The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit.
  • Page 106 USICLK bit clocks both the Shift Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 107 ATtiny25/45/85 Table 16-2 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 16-2. Relations between the USICS1..0 and USICLK Setting USICS1 USICS0 USICLK Shift Register Clock Source...

  • Page 108: Analog Comparator

    • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 109 When written logic zero, the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt.

  • Page 110: Analog Comparator Multiplexed Input

    PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 111: Analog To Digital Converter

    • Input Polarity Reversal Mode The ATtiny25/45/85 features a 10-bit successive approximation ADC. The ADC is connected to a 4-channel Analog Multiplexer which allows one differential voltage input and four single-ended voltage inputs constructed from the pins of Port B. The differential input (PB3, PB4 or PB2, PB5) is equipped with a programmable gain stage, providing amplification step of 26 dB (20x) on the differential input voltage before the A/D conversion.

  • Page 112: Operation

    1x or 20x, according to the setting of the MUX3..0 bits in ADMUX. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 113: Starting A Conversion

    ATtiny25/45/85 If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW.

  • Page 114: Prescaling And Conversion Timing

    200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency than 1 MHz. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 115 ATtiny25/45/85 The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA.
  • Page 116 Update Figure 18-7. ADC Timing Diagram, Free Running Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update ATtiny25/45/85 7598H–AVR–07/09...

  • Page 117: Changing Channel Or Reference Selection

    ATtiny25/45/85 Table 18-1. ADC Conversion Time Sample & Hold (Cycles from Total Conversion Time Condition Start of Conversion) (Cycles) First conversion 13.5 Normal conversions Auto Triggered conversions 13.5 18.5 Changing Channel or Reference Selection The MUX3..0 and REFS2..0 bits in the ADMUX Register are single buffered through a tempo- rary register to which the CPU has random access.

  • Page 118: Adc Noise Canceler

    Signal components higher than the Nyquist frequency (f /2) should not be present to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 119 ATtiny25/45/85 Figure 18-8. Analog Input Circuitry ADCn 1..100 kohm = 14 pF 18.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a.
  • Page 120 Figure 18-11. Integral Non-linearity (INL) Output Code Ideal ADC Actual ADC Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 121: Adc Conversion Result

    ATtiny25/45/85 Figure 18-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB 0x000 Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
  • Page 122 C and the accuracy of the temperature measurement ° is +/- C after bandgap calibration. 10° Table 18-2. Temperature vs. Sensor Output Voltage (Typical Case) Temperature / °C -45°C +25°C +105°C Voltage / mV 242 mV 314 mv 403 mV ATtiny25/45/85 7598H–AVR–07/09...
  • Page 123 ATtiny25/45/85 The values described in Table 51 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature measurement can be calibrated in the application soft- ware.
  • Page 124 ADC off while a conversion is in progress, will terminate this conversion. • Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 125 ATtiny25/45/85 The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the nor- mal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress.
  • Page 126 Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 127 10 bit unipolar measurement. • Bits 4..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.

  • Page 128: Debugwire On-Chip Debug System

    1.8 - 5.5V dW(RESET) Figure 19-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 129: Software Break Points

    ATtiny25/45/85 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional.

  • Page 130: Self-Programming The Flash

    SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 131: Performing A

    ATtiny25/45/85 20.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
  • Page 132 Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.
  • Page 133 ATtiny25/45/85 20.4.2 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register.

  • Page 134: Memory Programming

    This section describes the different methods for Programming the ATtiny25/45/85 memories. 21.1 Program And Data Memory Lock Bits The ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional security listed in Table 21-2.

  • Page 135: Fuse Bytes

    Notes: 1. Program the Fuse bits before programming the LB1 and LB2. 2. “1” means unprogrammed, “0” means programmed 21.2 Fuse Bytes The ATtiny25/45/85 has three Fuse bytes. Table 21-4, Table 21-5 and Table61 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.
  • Page 136 Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 137: Signature Bytes

    21.4 Calibration Byte Signature area of the ATtiny25/45/85 has one byte of calibration data for the internal RC Oscilla- tor. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.

  • Page 138: Serial Downloading

    >= 12 MHz 21.6.1 Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-2 Figure 21-3 for timing details.
  • Page 139 ATtiny25/45/85 To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 21-10): 1. Power-up sequence: Apply power between V and GND while RESET and SCK are set to “0”. In some sys- tems, the programmer can not guarantee that SCK is held low during power-up.
  • Page 140 Read data o from EEPROM 1010 000x xxbb oooo Memory memory at address b. 0000 xxxx bbbb oooo Write EEPROM Write data i to EEPROM 1100 000x xxbb iiii Memory memory at address b. 0000 xxxx bbbb iiii ATtiny25/45/85 7598H–AVR–07/09...
  • Page 141 ATtiny25/45/85 Table 21-10. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation 1100 0000 0000 iiii Load data i to EEPROM Load EEPROM 0001 0000 00bb iiii memory page buffer. After Memory Page (page...

  • Page 142: High-Voltage Serial Programming

    < 12 MHz, 3 t for f >= 12 MHz CLCL CLCL 21.7 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, Lock bits and Fuse bits in the ATtiny25/45/85. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 143 ATtiny25/45/85 Figure 21-4. High-voltage Serial Programming Table 21-12. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode Pin Name Function Serial Data Input Serial Instruction Input Serial Data Output Serial Clock Input (min. 220ns period) Table 21-13. High-voltage Serial Programming Characteristics T = 25°C ±10%,...

  • Page 144: High-Voltage Serial Programming Algorithm Sequence

    21.8 High-voltage Serial Programming Algorithm Sequence To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the fol- lowing sequence is recommended (See instruction formats in Table 21-16): 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1.
  • Page 145 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny25/45/85, data is clocked on the rising edge of the serial clock, see Figure...
  • Page 146 21.8.9 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 21-16. 21.8.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V power off. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 147 ATtiny25/45/85 Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr.3 until SDO goes Chip Erase 0_0100_1100_00 0_0110_0100_00 0_0110_1100_00 high for the Chip Erase cycle to finish.
  • Page 148 Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks 0_bbbb_bbbb_00 0_aaaa_aaaa_00 0_0000_0000_00 0_0000_0000_00 Repeat Instr. 1, 3 - 4 for each new Read EEPROM 0_0000_1100_00 0_0001_1100_00 0_0110_1000_00 0_0110_1100_00 address. Repeat Instr. 2 for a new Byte 256 byte page.

  • Page 149: High-Voltage Serial Programming Characteristics

    ATtiny25/45/85 21.9 High-voltage Serial Programming Characteristics Figure 21-7. High-voltage Serial Programming Timing Table 21-17. High-voltage Serial Programming Characteristics T = 25°C ±10%, = 5.0V ±10% (Unless otherwise noted) Symbol Parameter Units SCI (PB3) Pulse Width High SHSL SCI (PB3) Pulse Width Low...

  • Page 150: Electrical Characteristics

    = 5V Input Leakage Vcc = V, pin low Current I/O Pin except (absolute value) RESET Input Leakage Vcc = V, pin high Current I/O Pin except (absolute value) RESET Reset Pull-up Resistor kΩ I/O Pin Pull-up Resistor kΩ ATtiny25/45/85 7598H–AVR–07/09...

  • Page 151: External Clock Drive Waveforms

    ATtiny25/45/85 Table 22-1. DC Characteristics T = -40°C to 125°C, V = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units Active 4MHz, V = 3V 1.25 Active 8MHz, V = 5V Active 16MHz, V = 5V...

  • Page 152: External Clock Drive

    Change in period from one clock cycle to Δ CLCL the next Note: 1. All DC Characteristics contained in this data sheet result from actual silicon characterization. Figure 22-2. Maximum Frequency vs. V 16 MHz 8 MHz Safe Operating Area 2.7V 4.5V 5.5V ATtiny25/45/85 7598H–AVR–07/09...

  • Page 153: Adc Characteristics - Preliminary Data

    ATtiny25/45/85 22.4 ADC Characteristics – Preliminary Data Table 22-3. ADC Characteristics, Single Ended Channels. -40°C - 125°C. . PRELIMINARY Symbol Parameter Condition Units Resolution Single Ended Conversion Bits Single Ended Conversion = 4V, V = 4V, ADC clock = 200 kHz...

  • Page 154: Calibrated Rc Oscillator Accuracy

    The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential cur- rent drawn by the Watchdog Timer. ATtiny25/45/85 7598H–AVR–07/09...

  • Page 155: Active Supply Current

    ATtiny25/45/85 23.1 Active Supply Current Figure 23-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.040 5.5 V 0.035 5.0 V 0.030 4.5 V 4.0 V 0.025 0.020 3.3 V 2.7 V 0.015 0.010 0.005 0.000 Fre que nc y (MHz ) Figure 23-2.
  • Page 156 -40 ˚C 0.15 0.05 Figure 23-4. Active Supply Current vs. V (Internal RC Oscillator, 1 MHz) ACTIVE S UP P LY CURRENT vs . V INTERNAL RC OSCILLATOR, 1 MHz 125 ˚C 85 ˚C 25 ˚C -40 ˚C ATtiny25/45/85 7598H–AVR–07/09...

  • Page 157: Idle Supply Current

    ATtiny25/45/85 Figure 23-5. Active Supply Current vs. V (Internal RC Oscillator, 8 MHz) ACTIVE S UP P LY CURRENT vs . V INTERNAL RC OSCILLATOR, 8 MHz 125 ˚C 85 ˚C 25 ˚C -40 ˚C 23.2 Idle Supply Current Figure 23-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE S UP P LY CURRENT vs .
  • Page 158 Frequency (MHz) Figure 23-8. Idle Supply Current vs. V (Internal RC Oscillator, 128 kHz) IDLE S UP P LY CURRENT vs . V INTERNAL RC OSCILLATOR, 128 KHz 0.25 125 ˚C 85 ˚C 25 ˚C -40 ˚C 0.15 0.05 ATtiny25/45/85 7598H–AVR–07/09...
  • Page 159 ATtiny25/45/85 Figure 23-9. Idle Supply Current vs. V (Internal RC Oscillator, 1 MHz) IDLE S UP P LY CURRENT vs . V INTERNAL RC OSCILLATOR, 1 MHz 125 ˚C 85 ˚C 25 ˚C -40 ˚C Figure 23-10. Idle Supply Current vs. V (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs .
  • Page 160 23-9, we find that the idle current consumption is ~0,25mA at V = 3.0V and F = 1MHz. The total current consumption in idle mode with USI, TIMER0, and ADC enabled, gives: ≈ • ≈ 0,25 0,064 0,073 0,214 0,337mA total ATtiny25/45/85 7598H–AVR–07/09...

  • Page 161: Power-Down Supply Current

    ATtiny25/45/85 23.3 Power-Down Supply Current Figure 23-11. Power-Down Supply Current vs. V (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . V WATCHDOG TIMER DISABLED 125 ˚C 85 ˚C -40 ˚C 25 ˚C Figure 23-12. Power-Down Supply Current vs. V (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs .

  • Page 162: Pin Pull-Up

    Figure 23-14. I/O Pin Pull-Up Resistor Current vs. Input Voltage (V = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 2.7V 125 ˚C 85 ˚C 25 ˚C -40 ˚C ATtiny25/45/85 7598H–AVR–07/09...
  • Page 163 ATtiny25/45/85 Figure 23-15. I/O Pin Pull-Up Resistor Current vs. Input Voltage (V = 5.0V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 5.0V 125 ˚C 85 ˚C 25 ˚C -40 ˚C Figure 23-16. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V = 1.8V)
  • Page 164 Figure 23-18. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V = 5.0V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 5.0V 125 ˚C 85 ˚C 25 ˚C -40 ˚C RES ET ATtiny25/45/85 7598H–AVR–07/09...

  • Page 165: Pin Driver Strength

    ATtiny25/45/85 23.5 Pin Driver Strength Figure 23-19. I/O Pin Source Current vs. Output Voltage (V = 1.8V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE = 1.8V -40 ˚C 25 ˚C 85 ˚C 125 ˚C Figure 23-20. I/O Pin Source Current vs. Output Voltage (V = 3V) I/O P IN OUTP UT VOLTAGE vs .
  • Page 166 I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT Vc c = 5.0V Figure 23-22. I/O Pin Sink Current vs. Output Voltage (V = 1.8V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE = 1.8V 25 ˚C -40 ˚C 85 ˚C 125 ˚C ATtiny25/45/85 7598H–AVR–07/09...
  • Page 167 ATtiny25/45/85 Figure 23-23. I/O Pin Sink Current vs. Output Voltage (V = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT Vc c = 3V (mA) Figure 23-24. I/O Pin Sink Current vs. Output Voltage (V = 5.0V) I/O P IN OUTP UT VOLTAGE vs .

  • Page 168: Pin Thresholds And Hysteresis

    Figure 23-26. I/O Pin Input Threshold Voltage vs. V (VIL, I/O Pin Read As '0') I/O P IN INP UT THRES HOLD VOLTAGE vs . V VIL, IO PIN READ AS '0' 125 ˚C 85 ˚C 25 ˚C -40 ˚C ATtiny25/45/85 7598H–AVR–07/09...
  • Page 169 ATtiny25/45/85 Figure 23-27. I/O Pin Input Hysteresis vs. V I/O P IN INP UT HYS TERES IS -40 ˚C 25 ˚C 85 ˚C 125 ˚C Figure 23-28. Reset Input Threshold Voltage vs. V (VIH, Reset Pin Read As '1') RES ET INP UT THRES HOLD VOLTAGE vs . V VIH, IO PIN READ AS '1' 125 ˚C...
  • Page 170 25 ˚C -40 ˚C Figure 23-30. Reset Input Pin Hysteresis vs. V RES ET INP UT THRES HOLD VOLTAGE vs . V VIH, IO PIN READ AS '1' 0.25 0.15 0.05 125 ˚C 85 ˚C 25 ˚C -40 ˚C ATtiny25/45/85 7598H–AVR–07/09...

  • Page 171: Bod Thresholds And Analog Comparator Offset

    ATtiny25/45/85 23.7 BOD Thresholds and Analog Comparator Offset Figure 23-31. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL = 4.3V 4.35 Ris ing Falling 4.25 4.15 4.05 -50 -40 -30 -20 -10 90 100 110 120 130 140 Temperature (C) Figure 23-32.

  • Page 172: Internal Oscillator Speed

    90 100 110 120 130 140 Temperature (C) 23.8 Internal Oscillator Speed Figure 23-34. Watchdog Oscillator Frequency vs. V WATCHDOC OS CILLATOR FREQUENCY vs . V 0.118 0.116 -40 ˚C 0.114 25 ˚C 0.112 0.11 0.108 85 ˚C 0.106 0.104 125 ˚C 0.102 ATtiny25/45/85 7598H–AVR–07/09...
  • Page 173 ATtiny25/45/85 Figure 23-35. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OS CILLATOR FREQUENCY vs . TEMP ERATURE 0.118 0.116 0.114 0.112 0.11 0.108 1.8 V 0.106 2.7 V 0.104 3.6 V 4.0 V 0.102 5.5 V 100 110 120 Temperature Figure 23-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs .
  • Page 174 85 ˚C 25 ˚C -40 ˚C Figure 23-38. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 125 ˚C 85 ˚C 25 ˚C -40 ˚C OSCCAL (X1) ATtiny25/45/85 7598H–AVR–07/09...

  • Page 175: Current Consumption Of Peripheral Units

    ATtiny25/45/85 23.9 Current Consumption of Peripheral Units Figure 23-39. Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs . V 125 ˚C 85 ˚C 25 ˚C -40 ˚C Figure 23-40. Analog Comparator Current vs. V ANALOG COMP ARATOR CURRENT vs . V AREF = AVcc 150 ˚C...

  • Page 176: Current Consumption In Reset And Reset Pulse Width

    Pull-up) RES ET S UP P LY CURRENT vs . V 1 - 20 MHz , EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) ATtiny25/45/85 7598H–AVR–07/09...

  • Page 177: Analog To Digital Converter

    ATtiny25/45/85 Figure 23-43. Reset Pulse Width vs. V MINIMUM RES ET P ULS E WIDTH vs . V 2500 2000 1500 1000 125 ˚C 85 ˚C 25 ˚C -40 ˚C 23.11 Analog to Digital Converter Figure 23-44. Analog to Digital Converter Differential mode OFFSET vs. V...
  • Page 178 Figure 23-46. Analog to Digital Converter Differential mode GAIN vs. V Analog to Digital Converter - GAIN Differential Inputs , Vcc = 5V, Vref = 4V -1.2 -1.4 -1.6 Diff x20 -1.8 -2.2 -2.4 -2.6 Diff x1 -2.8 100 110 120 Temperature ATtiny25/45/85 7598H–AVR–07/09...
  • Page 179 ATtiny25/45/85 Figure 23-47. Analog to Digital Converter Single Endded mode GAIN vs. V Analog to Digital Converter - GAIN Single Ended, Vcc = 4V, Vref = 4V 100 110 120 -0.5 -1.5 -2.5 Temperature Figure 23-48. Analog to Digital Converter Differential mode DNL vs. V...
  • Page 180 Temperature Figure 23-50. Analog to Digital Converter differential mode INL vs. V Analog to Digital Converter - Integral Non Linearity INL Differential Inputs , Vcc = 4V, Vref = 4V Diff x20 Diff x1 100 110 120 Temperature ATtiny25/45/85 7598H–AVR–07/09...
  • Page 181 ATtiny25/45/85 Figure 23-51. Analog to Digital Converter Single Endded mode INL vs. V Analog to Digital Converter - Integral Non Linearity INL Single Ended, Vcc = 4V, Vref = 4V 0.72 0.68 0.66 0.64 0.62 0.58 100 110 120 Temperature...

  • Page 182: Register Summary

    3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATtiny25/45/85 7598H–AVR–07/09...
  • Page 183 ATtiny25/45/85 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x08 ACSR ACBG ACIE – ACIS1 ACIS0 page 108 0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 123...

  • Page 184: Instruction Set Summary

    I/O(P,b) ← 0 Clear Bit in I/O Register None Rd(n+1) ← Rd(n), Rd(0) ← 0 Logical Shift Left Z,C,N,V Rd(n) ← Rd(n+1), Rd(7) ← 0 Logical Shift Right Z,C,N,V Rotate Left Through Carry Rd(0)← C,Rd(n+1)← Rd(n),C← Rd(7) Z,C,N,V ATtiny25/45/85 7598H–AVR–07/09...
  • Page 185 ATtiny25/45/85 Mnemonics Operands Description Operation Flags #Clocks Rotate Right Through Carry Rd(7)← C,Rd(n)← Rd(n+1),C← Rd(0) Z,C,N,V Rd(n) ← Rd(n+1), n=0..6 Arithmetic Shift Right Z,C,N,V SWAP Swap Nibbles Rd(3..0)← Rd(7..4),Rd(7..4)← Rd(3..0) None SREG(s) ← 1 BSET Flag Set SREG(s) SREG(s) ← 0...

  • Page 186: Ordering Information

    26. Ordering Information Power Supply Speed (MHz) Ordering Code Package Operation Range ATtiny25/45/85-15ST Automotive (-40°C to +85°C) 2.7 - 5.5V 8 - 16 ATtiny25/45/85-15ST1 Automotive (-40°C to +105°C) ATtiny25/45/85-15SZ Automotive (-40°C to 125°C) ATtiny25/45/85-15MT Automotive (-40°C to 85°C) 2.7 - 5.5V...

  • Page 187: Packaging Information

    ATtiny25/45/85 27. Packaging Information 27.1 7598H–AVR–07/09...
  • Page 188 27.2 ATtiny25/45/85 7598H–AVR–07/09...

  • Page 189: Document Revision History

    ATtiny25/45/85 28. Document Revision History 28.1 Revision 7598H - 07/09 1. Absolute Maximum Ratings updated 28.2 Revision 7598G - 03/08 1. Modified See “Power Management and Sleep Modes” on page 31. 2. Modified See “MCU Control Register – MCUCR” on page 31.

  • Page 190: Errata

    29. Errata The revision letter in this section refers to the revision of the ATtiny25/45/85 device. 29.1 ATtiny25, Revision E 1. No known errata. Flash security improvements. 29.2 ATtiny45, Revision G 1. No known errata. Flash security improvements. 29.3 ATtiny85, Revision C 1.

  • Page 191: Table Of Contents

    Status Register ....................7 General Purpose Register File ................9 Stack Pointer ....................10 Instruction Execution Timing ................11 Reset and Interrupt Handling ................11 AVR ATtiny25/45/85 Memories ............. 13 In-System Re-programmable Flash Program Memory ........13 SRAM Data Memory ..................14 EEPROM Data Memory ..................15 I/O Memory ......................21 System Clock and Clock Options ............
  • Page 192 Internal Voltage Reference ................40 Watchdog Timer ....................41 8.10 Timed Sequences for Changing the Configuration of the Watchdog Timer ..44 Interrupts ....................45 Interrupt Vectors in ATtiny25/45/85 ..............45 10 I/O Ports ....................46 10.1 Introduction ......................46 10.2 Ports as General Digital I/O ................47 10.3...
  • Page 193 ATtiny25/45/85 12.3 Counter Unit ....................62 12.4 Output Compare Unit ..................63 12.5 Compare Match Output Unit ................65 12.6 Modes of Operation ..................66 12.7 Timer/Counter Timing Diagrams ..............70 12.8 8-bit Timer/Counter Register Description ............72 13 Timer/Counter Prescaler ............... 78 13.1 Prescaler Reset ....................78 13.2...
  • Page 194 23.2 Idle Supply Current ..................157 23.3 Power-Down Supply Current .................161 23.4 Pin Pull-up .....................162 23.5 Pin Driver Strength ..................165 23.6 Pin Thresholds and Hysteresis ..............168 23.7 BOD Thresholds and Analog Comparator Offset ..........171 23.8 Internal Oscillator Speed ................172 ATtiny25/45/85 7598H–AVR–07/09...
  • Page 195 28.7 Revision 7598B - 08/06 .................189 28.8 Changes from Revision 2535A-09/01 to Revision 7598A-04/06 ....189 29 Errata ..................... 190 29.1 ATtiny25, Revision E ..................190 29.2 ATtiny45, Revision G ..................190 29.3 ATtiny85, Revision C ..................190 30 Table of Contents ................. 191...
  • Page 196 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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