Atmel AT91CAP9A-DK User Manual
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Atmel AT91CAP9A-DK User Manual

Atmel AT91CAP9A-DK User Manual

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AT91CAP9A-DK Development Kit
....................................................................................................................
User Guide
6321B–CAP–02-Jul-07

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Summary of Contents for Atmel AT91CAP9A-DK

  • Page 1 AT91CAP9A-DK Development Kit ........................User Guide 6321B–CAP–02-Jul-07...
  • Page 2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 3: Table Of Contents

    I2S ........................3-4 Analog Interface......................... 3-4 3.10 User Interface ........................3-4 3.11 Debug Interface ......................... 3-5 3.12 Memory Expansion Slots ....................3-5 3.13 PIO Connectors ......................... 3-5 3.14 FPGA Extension ........................ 3-5 3.14.1 Overview......................3-5 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 4 Host USB Port........................7-5 FPGA Connections ......................7-5 7.7.1 FPGA Banking Allocations................... 7-5 7.7.2 CAP/MPIO Bus Connections ................7-5 7.7.3 SODIMM Connection................... 7-9 7.7.4 PISMO-II Connector ..................7-13 7.7.5 User LEDs and I/O Grid..................7-22 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 5 13.1 Electrostatic Warning ....................... 13-1 13.2 Requirements........................13-1 13.3 Layout ..........................13-1 13.4 Powering Up the Board....................13-2 Section 14 AT91CAP-MEM33 Configuration ................14-1 14.1 Configuration........................14-1 Section 15 AT91CAP-DKM Schematics..................15-1 15.1 Schematics ........................15-1 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 6 17.1 Schematics ........................17-1 Section 18 AT91CAP-MEM33 Schematics ................18-1 18.1 Schematics ........................18-1 Section 19 Errata........................19-1 19.1 Known Errata ........................19-1 Section 20 Revision History ....................... 20-1 20.1 Revision History ....................... 20-1 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 7: At91Cap9A-Dk Development Board And At91Cap-Dkm Motherboard Overview

    Motherboard, Mezzanine and Memory Extension to be used jointly in order to develop AT91CAP9 processor applications. The AT91CAP9A-DK development board implements the fixed portion of the AT91CAP9 device as a microcontroller standard product, tightly coupled to a high-density FPGA that emulates the MP Block.

  • Page 8: Purpose

    Overview of AT91CAP9A-DK Development Kit/AT91CAP-DKM Motherboard Memory extension CAP Mezzanine Motherboard Purpose The AT91CAP-DKM Motherboard provides all the service items of an AT91CAP9A-DK development system. That is: Power supply input, conversion and distribution, Standard user interfaces, Prototyping interface and extension means.

  • Page 9: Setting Up The At91Cap-Dkm Motherboard

    Avoid touching the component pins or any other on-board metallic element. Requirements In order to set up an AT91CAP9A-DK development system, the following items are needed: AT91CAP-DKM motherboard PC/ATX standard power supply unit AT91CAP9A-DKZ mezzanine board (see Sections 5 through 8), with a memory extension (see...

  • Page 10: Powering Up The Board

    ISI interface Powering Up the Board A complete AT91CAP9A-DK system is powered through the AT91CAP-DKM motherboard via a stan- dard ATX PC power supply. The power control signal is connected to the SHDN signal, generated by the AT91CAP9 chip from the AT91CAP9A-DKZ mezzanine board.

  • Page 11: At91Cap-Dkm Motherboard

    Section 3 AT91CAP-DKM Motherboard AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 12: Block Diagram

    Block Diagram Figure 3-1. AT91CAP-DKM Motherboard (see the complete schematic in Section 15, “AT91CAP-DKM Schematics” AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 13: Clock Circuity

    1.2V 1.8V 2.5V Memory The only memory resource available on the AT91CAP-DKM motherboard is an Atmel serial EEPROM (TWI bus connection). System memory resources are to be connected directly to the AT91CAP9A-DKZ mezzanine via the AT91CAP9-MEMxx extension boards. Remote Communication 3.7.1...

  • Page 14: Device Usb Interface

    4x4 keypad: uses 8 PIO lines in a matrix scheme, each button shunts two of them Two green LEDs One yellow power LED (note that it is software controlled) One 3.5 inch VGA display LCD with Touch Panel and white LED backlight AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 15: Debug Interface

    J9 = PCI64 female connector for FPGA I/O expansion J8/J10 = two 200-pin connectors for “Mistral” extension board Warning: FPGA IOs are distributed among J8, J9 and J10 connectors and also the three USB device ports, some having dual connections as follows: AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 16: At91Cap-Dkm Extension Connectors

    3.14.2 AT91CAP-DKM Extension Connectors Figure 3-2. J8 and J10 (Top View) J8 and J10 as seen on AT91CAP9-DKM from above 3.14.3 “Mistral” Extension Connectors Pins not listed in Table 3-2 below are not connected. AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 17 DIFFIO_TX28n FPGA7 DIFFIO_RX27p FPGA8 DIFFIO_RX27n FPGA9 DIFFIO_TX27p FPGA10 DIFFIO_TX27n FPGA11 DIFFIO_RX26p AA32 FPGA12 DIFFIO_RX26n AA31 FPGA13 DIFFIO_TX26p FPGA14 DIFFIO_TX26n FPGA15 DIFFIO_RX25p FPGA16 DIFFIO_RX25n FPGA17 DIFFIO_TX25p FPGA18 DIFFIO_TX25n FPGA19 DIFFIO_RX24p AB32 FPGA20 DIFFIO_RX24n AB31 FPGA21 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 18 DIFFIO_TX22p FPGA30 DIFFIO_TX22n FPGA31 DIFFIO_RX21p AB30 FPGA32 DIFFIO_RX21n AB29 FPGA33 DIFFIO_TX21p FPGA34 DIFFIO_TX21n FPGA35 DIFFIO_RX20p AC32 FPGA36 DIFFIO_RX20n AC31 FPGA37 DIFFIO_TX20p AA27 FPGA38 DIFFIO_TX20n AA26 FPGA39 DIFFIO_RX19p AB28 FPGA40 DIFFIO_RX19n AB27 FPGA41 DIFFIO_TX19p FPGA42 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 19 AF32 FPGA52 DIFFIO_RX16n AF31 FPGA53 DIFFIO_TX16p AC27 FPGA54 DIFFIO_TX16n AC26 FPGA55 DIFFIO_RX15p AG32 FPGA56 NRST DIFFIO_RX15n AG31 FPGA57 DIFFIO_TX15p FPGA58 DIFFIO_TX15n FPGA59 DIFFIO_RX14p AC30 FPGA60 DIFFIO_RX14n AC29 FPGA61 DIFFIO_TX14p AA25 FPGA62 DIFFIO_TX14n AA24 FPGA63 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 20 DIFFIO_TX11p AB24 FPGA74 DIFFIO_TX11n AB23 FPGA75 DIFFIO_RX10p AJ32 FPGA76 DIFFIO_RX10n AJ31 FPGA77 DIFFIO_TX10p AC25 FPGA78 DIFFIO_TX10n AC24 FPGA79 DIFFIO_RX9p AF30 FPGA80 DIFFIO_RX9n AF29 FPGA81 DIFFIO_TX9p AD25 FPGA82 DIFFIO_TX9n AD24 FPGA83 DIFFIO_RX8p AG30 FPGA84 3-10 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 21 FPGA91 DIFFIO_RX6p AF28 FPGA92 DIFFIO_RX6n AF27 FPGA93 DQS16T FPGA252 DQS17T FPGA260 DQ17T FPGA261 DQ17T FPGA262 DIFFIO_TX51p FPGA98 DIFFIO_TX51n FPGA99 DIFFIO_RX50p FPGA100 DIFFIO_RX50n FPGA101 DIFFIO_TX50p FPGA102 DIFFIO_TX50n FPGA103 DIFFIO_RX49p FPGA104 DIFFIO_RX49n FPGA105 DIFFIO_TX49p FPGA106 AT91CAP9A-DK Development Kit User Guide 3-11 6321B–CAP–02-Jul-07...
  • Page 22 Table 3-3. J10 (female) Pin Assignment Table FPGA FPGA Pin Other FPGA Pin J10 Pin Bank Function Information FPGA Ball Board Net DIFFIO_TX46p FPGA118 DIFFIO_TX46n FPGA119 DIFFIO_RX45p FPGA120 DIFFIO_RX45n FPGA121 DIFFIO_TX45p FPGA122 DIFFIO_TX45n FPGA123 DIFFIO_RX44p FPGA124 3-12 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 23 FPGA130 DIFFIO_TX43n FPGA131 DIFFIO_RX42p FPGA132 DIFFIO_RX42n FPGA133 DIFFIO_TX42p FPGA134 DIFFIO_TX42n FPGA135 DIFFIO_RX41p FPGA136 DIFFIO_RX41n FPGA137 DIFFIO_TX41p FPGA138 DIFFIO_TX41n FPGA139 DIFFIO_RX40p FPGA140 DIFFIO_RX40n FPGA141 DIFFIO_TX40p FPGA142 DIFFIO_TX40n FPGA143 DIFFIO_RX39p FPGA144 DIFFIO_RX39n FPGA145 DIFFIO_TX39p FPGA146 AT91CAP9A-DK Development Kit User Guide 3-13 6321B–CAP–02-Jul-07...
  • Page 24 FPGA151 DIFFIO_RX37p FPGA152 DIFFIO_RX37n FPGA153 DIFFIO_TX37p FPGA154 DIFFIO_TX37n FPGA155 DIFFIO_RX36p FPGA156 DIFFIO_RX36n FPGA157 DIFFIO_TX36p FPGA158 DIFFIO_TX36n FPGA159 DIFFIO_RX35p FPGA160 DIFFIO_RX35n FPGA161 DIFFIO_TX35p FPGA162 DIFFIO_TX35n FPGA163 DIFFIO_RX34p FPGA164 DIFFIO_RX34n FPGA165 DIFFIO_TX34p FPGA166 DIFFIO_TX34n FPGA167 3-14 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 25 DIFFIO_TX32p FPGA174 CLK1p INPUT FPGA175 DIFFIO_RX31p FPGA176 DIFFIO_RX31n FPGA177 DIFFIO_TX31p FPGA178 DIFFIO_TX31n FPGA179 DIFFIO_RX30p FPGA180 DIFFIO_RX30n FPGA181 DIFFIO_TX30p FPGA182 DIFFIO_TX30n FPGA183 DIFFIO_RX29p FPGA184 DIFFIO_RX29n FPGA185 DIFFIO_TX29p FPGA186 DIFFIO_TX29n FPGA187 CLK0n/DIFFIO_RX_C0n FPGA188 CLK0p/DIFFIO_RX_C0p FPGA189 AT91CAP9A-DK Development Kit User Guide 3-15 6321B–CAP–02-Jul-07...
  • Page 26 FPGA270 DIFFIO_TX32n FPGA191 CLK14p FPGA192 CLK14n FPGA193 CLK15p FPGA194 CLK15n FPGA195 FPGA196 FPGA197 FPGA198 FPGA199 FPGA200 FPGA201 DQS10T FPGA202 DQ10T FPGA203 DQ10T FPGA204 DQ10T FPGA205 DQSn10T FPGA206 DQ10T FPGA207 FPGA208 FPGA209 FPGA210 FPGA211 3-16 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 27 Board Net DQS11T FPGA212 DQ11T FPGA213 DQ11T FPGA214 DQ11T FPGA215 DQSn11T FPGA216 DQ11T FPGA217 FPGA218 FPGA219 FPGA220 DQS12T FPGA221 DQ12T FPGA222 DQ12T FPGA223 DQ12T FPGA224 DQSn12T FPGA225 DQ12T FPGA226 FPGA227 FPGA228 VCCIO1 VCCIO2 VCCIO3 AT91CAP9A-DK Development Kit User Guide 3-17 6321B–CAP–02-Jul-07...
  • Page 28 FPGA FPGA Pin J9 Pin Bank Function Other FPGA Pin Information FPGA Ball Board Net DIFFIO_TX31n FPGA179 -12VPCI 12VPCI DIFFIO_RX31p FPGA176 DIFFIO_RX31n FPGA177 DIFFIO_TX31p FPGA178 CLK1p INPUT FPGA175 5VPCI 5VPCI DIFFIO_RX30p FPGA180 5VPCI 3-18 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 29 DIFFIO_TX29p FPGA186 DIFFIO_TX29n FPGA187 CLK1n INPUT FPGA190 VCCIO2 CLK0p/DIFFIO_RX_C0p FPGA189 CLK0n/DIFFIO_RX_C0n FPGA188 VCCIO2 DIFFIO_TX32n FPGA191 CLK14p FPGA192 CLK14n FPGA193 CLK15p FPGA194 CLK15n FPGA195 FPGA196 VCCIO3 FPGA197 FPGA198 VCCIO3 FPGA199 FPGA200 FPGA201 DQS10T FPGA202 AT91CAP9A-DK Development Kit User Guide 3-19 6321B–CAP–02-Jul-07...
  • Page 30 FPGA207 FPGA208 FPGA209 FPGA210 VCCIO3 FPGA211 DQS11T FPGA212 VCCIO3 DQ11T FPGA213 DQ11T FPGA214 DQ11T FPGA215 DQSn11T FPGA216 VCCIO3 DQ11T FPGA217 FPGA218 VCCIO3 FPGA219 FPGA220 VCCIO3 DQS12T FPGA221 DQ12T FPGA222 DQ12T FPGA223 DQ12T FPGA224 3-20 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 31 DQS13T FPGA229 DQ13T FPGA230 VCCIO3 DQ13T FPGA231 DQ13T FPGA232 DQSn13T FPGA233 DQ13T FPGA234 FPGA235 FPGA236 VCCIO3 VCCIO3 FPGA237 DQS14T FPGA238 5VPCI 5VPCI 5VPCI 5VPCI DQ14T FPGA239 DQ14T FPGA240 DQ14T FPGA241 VCCIO3 DQSn14T FPGA242 AT91CAP9A-DK Development Kit User Guide 3-21 6321B–CAP–02-Jul-07...
  • Page 32 DQ15T FPGA250 FPGA251 DQS16T FPGA252 DQ16T FPGA253 VCCIO3 DQ16T FPGA254 DQ16T FPGA255 DQSn16T FPGA256 DQ16T FPGA257 FPGA258 FPGA259 VCCIO3 DQS17T FPGA260 DQ17T FPGA261 DQ17T FPGA262 DQ17T FPGA263 DQSn17T FPGA264 DQ17T FPGA265 VCCIO3 FPGA266 3-22 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 33: Usb Device Interfaces

    Table 3-5. USB Interface and FPGA Connection FPGA FPGA Board Bank Ball Board Signal Component Function FPGA246 VBUS detection FPGA247 FPGA248 SUSPEND FPGA2 FPGA3 AJ29 FPGA94 FPGA253 VMO/FSEO FPGA254 VPO/VO FPGA255 SOFTCON FPGA256 VBUS detection AT91CAP9A-DK Development Kit User Guide 3-23 6321B–CAP–02-Jul-07...

  • Page 34: At91Cap9 Mezzanine Extension

    SD/MMC/DATAFLASH SOCKET (J28) MCI0_CDA/SPI0_MOSI VDDIOP0 MCI0_CK SPI0_SPCK SD/MMC/DATAFLASH SOCKET (J28) MCI0_CK/SPI0_SPCK VDDIOP0 MCI0_DA1 SPI0_NPCS1 SD/MMC/DATAFLASH SOCKET (J28) MCI0_DA1 VDDIOP0 MCI0_DA2 SPI0_NPCS2 SD/MMC/DATAFLASH SOCKET (J28) MCI0_DA2 VDDIOP0 MCI0_DA3 SPI0_NPCS0 SD/MMC/DATAFLASH SOCKET (J28) MCI0_DA3/SPI0_NPCS0 VDDIOP0 3-24 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 35 Peripheral B Peripheral Usage I2S CODEC (MN14) VDDIOP0 I2S CODEC (MN14) VDDIOP0 I2S CODEC (MN14) VDDIOP0 I2S CODEC (MN14) VDDIOP0 I2C MEMORY (MN10), ISI (J27) VDDIOP0 TWCK I2C MEMORY (MN10), ISI (J27) TWCK VDDIOP0 AT91CAP9A-DK Development Kit User Guide 3-25 6321B–CAP–02-Jul-07...
  • Page 36 SSC0. 2. Factory setting. Figure 3-1 3. Please refer to the board's diagram, . The AT91CAP9 chip has 8 ADC channels, only 4 of which can be buffered at a time. 3-26 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 37 LCD PANEL CONNECTOR (J37) PWM0 as VCTRL VDDIOP0 PC29 PCK0 PWM2 POWER LED CONTROL (DS3) PC29 or PWM2 VDDIOP0 PC30 DRXD DBGU RS232 INTERFACE (J23) DRXD VDDIOP0 PC31 DTXD DBGU RS232 INTERFACE (J23) DTXD VDDIOP0 AT91CAP9A-DK Development Kit User Guide 3-27 6321B–CAP–02-Jul-07...
  • Page 38 PD21 EBI_D21 VDDIOM PD22 EBI_D22 VDDIOM PD23 EBI_D23 VDDIOM PD24 EBI_D24 VDDIOM PD25 EBI_D25 VDDIOM PD26 EBI_D26 VDDIOM PD27 EBI_D27 VDDIOM PD28 EBI_D28 VDDIOM PD29 EBI_D29 VDDIOM PD30 EBI_D30 VDDIOM PD31 EBI_D31 VDDIOM 3-28 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 39: At91Cap-Dkm Configuration

    R153,154 - use alternate J25 - apply CAN input channel of I2S chip termination J2 - TouchScreen R93,94,95 - J11,13,15 - Chip Select choice VDDIOP1 voltage FPGA USB interfaces selection speed selection Configuration Jumpers and Straps AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 40 Selects ISP1105BS PHY MN4 mode input. Please refer to the datasheet of this device for in- R18, 19 ON, OFF depth details. Selects ISP1105BS PHY MN5 mode input. Please refer to the datasheet of this device for in- R27, 28 ON, OFF depth details. AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 41 3. Refer to to see the span of this IO bank (J8, 9, 10 connectors). By default this voltage is fixed at 3.3V. Change this setting only if you are sure of what you are doing...! AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 42 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 43: Overview At91Cap9A-Dkz Mezzanine

    (AT91CAP9A-DKZ). Figure 5-1. AT91CAP9A-DKZ Overview Memory extension AT91CAP9A-DKZ Mezzanine Motherboard Purpose The AT91CAP9A-DKZ mezzanine provides a configurable processor (AT91CAP9) and its associated FPGA, both being at the heart of an AT91CAP9A-DK development system layout. AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 44 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 45: Setting Up The At91Cap9A-Dkz Mezzanine

    Avoid touching the component pins or any other on-board metallic element. Requirements In order to set up an AT91CAP9A-DK development system, the following items are needed: AT91CAP9A-DKZ mezzanine Memory extension board (see sections 9 through 14)

  • Page 46: Fpga Specific (Altera Stratix-Ii Ep2S90F1020C5)

    SODIMM-144 format Powering Up the Board A complete AT91CAP9A-DK system is powered through the AT91CAP-DKM motherboard via a stan- dard ATX PC power supply. The power control signal is connected to the SHDN signal, generated by the AT91CAP9 chip from the AT91CAP9A-DKZ mezzanine board.

  • Page 47: At91Cap9A-Dkz Mezzanine Board

    Section 7 AT91CAP9A-DKZ Mezzanine Board AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 48: Block Diagram

    Block Diagram Figure 7-1. AT91CAP9A-DKZ Mezzanine Block Diagram (see the complete schematic in Section PISMO2 CAP_SODIMM MOTHERBOARD CONNECTORS AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 49 FPGA EBI bus (89) JTAG header (except TDO) USER IO GRID bus (72) FPGA PISMO-II bus (214) JTAG TDO config memory USER IO bus (276) 12MHz TCXO ByteBlaster header (down to motherboard) SAMTEC SEAF-40-05.0-SM-8-2-A-K AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 50: Reset Path

    System memory resources are provided via extension boards in SODIMM-144 format. There is one each for the AT91CAP9 and the FPGA chips. These connections are labeled “EBI”, named after the Atmel standard “External Bus Interface”. Note that the bus voltage of each of these extensions is automatically customizable: An adjustable regulator located on the mezzanine board, provides the bus voltage.

  • Page 51: Host Usb Port

    AG25 MPIOA01 AB21 MPIOA02 AE22 MPIOA03 AF22 MPIOA04 AD22 MPIOA05 AH28 DQ17B MPIOA06 AK29 DQSn17B MPIOA07 AJ28 DQ17B MPIOA08 AM29 DQ17B MPIOA09 AL29 DQ17B MPIOA10 AK28 DQS17B MPIOA11 AC21 MPIOA12 AG21 MPIOA13 AK27 DQ16B AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 52 MPIOB07 AK24 DQ13B MPIOB08 AK23 DQ13B MPIOB09 AM23 DQ13B MPIOB10 AL23 DQS13B MPIOB11 AD20 MPIOB12 AG23 DQ12B MPIOB13 AH22 DQSn12B MPIOB14 AG22 DQ12B MPIOB15 AK22 DQ12B MPIOB16 AJ23 DQ12B MPIOB17 AJ22 DQS12B MPIOB18 AC20 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 53 MPIOB35 AJ19 DQ10B MPIOB36 AH19 DQ10B MPIOB37 AL20 DQ10B MPIOB38 AK20 DQS10B MPIOB39 AC18 MPIOB40 AD18 MPIOB41 AB17 MPIOB42 AC17 MPIOB43 AJ17 CLK5n MPIOB44 AL17 CLK4n Note: 1. MPIOB24 is the MPIO bus clock. AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 54: Sodimm Connection

    DQ4B SODIMM_D06 AH11 DQ6B SODIMM_D14 DQ4B SODIMM_D07 AJ11 DQ6B SODIMM_D15 AJ10 DQ4B SODIMM_D16 DQSn3B SODIMM_D24 DQSn1B SODIMM_D17 DQ3B SODIMM_D25 DQ1B VCCIO_7 VCCIO_7 SODIMM_D18 DQ3B SODIMM_D26 DQ1B SODIMM_D19 DQ3B SODIMM_D27 DQ1B SODIMM_D20 DQ2B SODIMM_D28 DQ0B AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 55 DQ9B SODIMM_C30 DQS4B SODIMM_C04 AL13 DQSn9B SODIMM_C31 AC13 SODIMM_C05 AJ13 DQ9B SODIMM_C32 AE12 SODIMM_C06 AJ14 DQ9B SODIMM_C33 DQ3B VCCIO_7 VCCIO_7 SODIMM_C07 AL14 DQ9B SODIMM_C34 DQS3B SODIMM_C08 AK13 DQS9B SODIMM_C35 AB13 SODIMM_C09 AD14 SODIMM_C36 AD12 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 56 SODIMM_C44 AC11 SODIMM_C18 AF14 SODIMM_C45 AB12 SODIMM_C19 AM12 DQ7B SODIMM_C46 AE10 SODIMM_C20 AL11 DQS7B SODIMM_C47 AB11 RDN7 SODIMM_C21 AC14 SODIMM_C48 AD10 VCCIO_7 VCCIO_7 SODIMM_C22 AK11 DQSn6B SODIMM_C49 SODIMM_C23 AK10 DQS6B SODIMM_C50 AH16 CLK7p 7-10 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 57 SODIMM_S01 AA10 DIFFIO_TX102p SODIMM_S11 DIFFIO_RX100p SODIMM_S02 DIFFIO_RX102n SODIMM_S12 DIFFIO_TX99n SODIMM_S03 DIFFIO_RX102p SODIMM_S13 DIFFIO_TX99p VCCIO_6 VCCIO_6 SODIMM_S04 DIFFIO_TX101n SODIMM_S14 DIFFIO_RX99n SODIMM_S05 DIFFIO_TX101p SODIMM_S15 DIFFIO_RX99p SODIMM_S06 DIFFIO_RX101n SODIMM_S16 DIFFIO_TX98n SODIMM_S07 DIFFIO_RX101p SODIMM_S17 DIFFIO_TX98p SODIMM_S08 DIFFIO_TX100n AT91CAP9A-DK Development Kit User Guide 7-11 6321B–CAP–02-Jul-07...

  • Page 58: Pismo-Ii Connector

    PISMO_DM_DC0 DQ4T DM_D19 PISMO_DM_DC3 DQ4T DM_D22 PISMO_DM_DC6 DQ5T DM_D23 PISMO_DM_DC7 DQ5T DM_DQS2_DH PISMO_DM_DQSC_DH DQS4T VSS20 SM_D23 PISMO_SM70 DIFFIO_TX71n SM_D22 PISMO_SM69 DIFFIO_RX72p SM_D21 PISMO_SM68 DIFFIO_RX72n SM_D20 PISMO_SM67 DIFFIO_TX72p SM_D19 PISMO_SM66 DIFFIO_TX72n SM_D18 PISMO_SM65 DIFFIO_RX73p 7-12 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 59 PISMO_DM_DA2 DQ0T DM_D04 PISMO_DM_DA4 DQ1T DM_D07 PISMO_DM_DA7 DQSn1T DM_DQS0_DL PISMO_DM_DQSA_DL DQSn0T DM_D17 PISMO_DM_DC1 DQ4T DM_D18 PISMO_DM_DC2 DQ4T DM_D20 PISMO_DM_DC4 DQS5T DM_D21 PISMO_DM_DC5 DQ5T DM_DQS2_DL PISMO_DM_DQSC_DL DQSn4T VSS21 SM_D31 PISMO_SM79 DIFFIO_TX69p SM_D30 PISMO_SM78 DIFFIO_TX69n AT91CAP9A-DK Development Kit User Guide 7-13 6321B–CAP–02-Jul-07...
  • Page 60 DM_VIO_3 VCCIO_4 DM_VIO_6 VCCIO_4 DM_VIO_5 VCCIO_4 DM_VIO_8 VCCIO_4 DM_VIO_4 VCCIO_4 Section 16 DM_VCC_3 (see schematics, DM_VIO_2 VCCIO_4 DM_VIO_7 VCCIO_4 Section 16 DM_VCC_2 (see schematics, Section 16 DM_VCC_1 (see schematics, DM_VIO_1 VCCIO_4 DM_VIO_0 VCCIO_4 7-14 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 61 DM_CS1# PISMO_DM27 DQS8T DM_A15 PISMO_DM15 DM_A07 PISMO_DM07 DM_A11 PISMO_DM11 DM_CKE1 PISMO_DM21 DM_A14 PISMO_DM14 DQ3T DM_A08 PISMO_DM08 DQS1T DM_DQM1 PISMO_DM29 DQ8T VSS37 DM_CLK1_DH PISMO_DM24 DQSn7T VSS34 DM_CLK0_DH PISMO_DM22 VSS31 DM_A10 PISMO_DM10 DM_WE# PISMO_DM36 DQ9T AT91CAP9A-DK Development Kit User Guide 7-15 6321B–CAP–02-Jul-07...
  • Page 62 SM_A02 PISMO_SM02 DIFFIO_TX88n CLK10p/DIFFIO_ SM_A00 PISMO_SM00 RX_C3p SM_BE0# PISMO_SM32 DIFFIO_RX81n VSS46 DM_A04 PISMO_DM04 DM_A06 PISMO_DM06 DM_A09 PISMO_DM09 DQ1T DM_CKE0 PISMO_DM20 DQ5T DM_DQM3 PISMO_DM31 DQSn8T DM_A12 PISMO_DM12 DM_A05 PISMO_DM05 VSS38 DM_CLK1_DL PISMO_DM25 DQ7T VSS35 7-16 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 63 PISMO_SM13 DIFFIO_RX86p SM_A11 PISMO_SM11 DIFFIO_TX86p SM_A09 PISMO_SM09 DIFFIO_RX87p SM_A07 PISMO_SM07 DIFFIO_TX87p SM_A05 PISMO_SM05 DIFFIO_RX88p SM_A03 PISMO_SM03 DIFFIO_TX88p CLK10n/DIFFIO_ SM_A01 PISMO_SM01 RX_C3n SM_BE1# PISMO_SM33 DIFFIO_RX81p FS_SCK PISMO_FS06 VSS45 FS_V33_0 3.3V VSS44 VSS43 VSS42 VSS41 AT91CAP9A-DK Development Kit User Guide 7-17 6321B–CAP–02-Jul-07...
  • Page 64 3.3V NA_V18_0 1.8V VSS15 VSS14 SM_OE# PISMO_SM84 DIFFIO_RX68n SM_WE# PISMO_SM74 DIFFIO_TX70n SM_LBA# PISMO_SM83 DIFFIO_TX68p SM_BUSY# PISMO_SM36 DIFFIO_RX80n SM_BWAIT# PISMO_SM37 DIFFIO_RX80p VSS4 VSS3 VSS2 VSS1 VSS0 FS_SO PISMO_FS08 CLK12p FS_SI PISMO_FS07 CLK12n DNU9 n.c. 7-18 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 65 NA_RY PISMO_NA24 DIFFIO_RX105n NA_CS2# PISMO_NA04 DIFFIO_RX110n NA_CS1# PISMO_NA03 DIFFIO_TX110p NA_CLE PISMO_NA01 DIFFIO_RX111p NA_WE# PISMO_NA25 DIFFIO_RX105p DNU5 n.c. VSS11 VSS8 VSS7 VSS6 VSS5 DNU1 n.c. SM_IRQ# PISMO_SM81 DIFFIO_RX69p SM_CRE PISMO_SM42 DIFFIO_TX78n SM_DMARQ# PISMO_SM80 DIFFIO_RX69n AT91CAP9A-DK Development Kit User Guide 7-19 6321B–CAP–02-Jul-07...
  • Page 66 PISMO_NA22 AB10 DIFFIO_TX105n NA_RE# PISMO_NA23 DIFFIO_TX105p NA_CS3# PISMO_NA05 DIFFIO_RX110p NA_CS0# PISMO_NA02 DIFFIO_TX110n NA_ALE PISMO_NA00 DIFFIO_RX111n NA_WP# PISMO_NA26 DIFFIO_TX104n DNU6 n.c. DNU4 n.c. DNU3 n.c. SM_WP# PISMO_SM82 DIFFIO_TX68n SM_RESET# PISMO_SM86 DIFFIO_TX67n SM_PD PISMO_SM85 DIFFIO_RX68p 7-20 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 67: User Leds And I/O Grid

    Board Signal Name FPGA Bank AC22 UGRID00 CLKUSR AD23 UGRID01 AE23 UGRID02 AF23 UGRID03 RUnLU AG17 UGRID04 DEV_OE AH17 UGRID05 DEV_CLRn AG19 UGRID06 AG18 UGRID07 PLL12_FBn/OUT2n AL19 UGRID08 PLL12_FBp/OUT2p AM19 UGRID09 PLL12_OUT1n AH18 UGRID10 AT91CAP9A-DK Development Kit User Guide 7-21 6321B–CAP–02-Jul-07...
  • Page 68 UGRID31 DIFFIO_TX95p UGRID32 DIFFIO_RX95n UGRID33 DIFFIO_RX95p UGRID34 DIFFIO_TX94n UGRID35 DIFFIO_TX94p UGRID36 DIFFIO_RX94n UGRID37 DIFFIO_RX94p UGRID38 DIFFIO_TX93n UGRID39 DIFFIO_TX93p UGRID40 DIFFIO_RX93n UGRID41 DIFFIO_RX93p UGRID42 DIFFIO_TX92n UGRID43 DIFFIO_TX92p UGRID44 DIFFIO_RX92n UGRID45 DIFFIO_RX92p UGRID46 DIFFIO_TX91n UGRID47 7-22 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 69 UGRID61 CLK8p/DIFFIO_RX_C2p UGRID62 PLL5_FBn/OUT2n UGRID63 PLL5_FBp/OUT2p UGRID64 PLL5_OUT0n UGRID65 PLL5_OUT0p UGRID66 PLL5_OUT1n UGRID67 PLL5_OUT1p UGRID68 PLL11_OUT0p UGRID69 PLL11_OUT0n UGRID70 PLL11_OUT1p UGRID71 PLL11_OUT1n UGRID72 PLL11_FBp/OUT2p UGRID73 PLL11_FBn/OUT2n UGRID74 INIT_DONE UGRID75 Note: 1. FPGA-input-only pin. AT91CAP9A-DK Development Kit User Guide 7-23 6321B–CAP–02-Jul-07...
  • Page 70 AC10 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT 7-24 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 71 VCCPD7 AA15 VCCPD8 AA18 VCCPD8 AA20 VCCPD4 VCCPD4 VCCPD3 VCCPD3 VCCPD5 VCCPD2 VCCPD5 VCCPD2 VCCPD6 VCCPD1 VCCPD6 VCCPD1 AA14 AA19 AA21 AB22 AC28 GNDA_PLL6 AD16 GNDA_PLL12 AD17 GNDA_PLL6 AE16 GNDA_PLL12 AE17 AF17 GNDA_PLL9 AT91CAP9A-DK Development Kit User Guide 7-25 6321B–CAP–02-Jul-07...
  • Page 72 Bank Pin Type Name Other Pin Information Function Ball Board Net GNDA_PLL8 AG26 GNDA_PLL8 AG27 GNDA_PLL9 AH10 AH23 AH27 AL32 AM13 AM20 AM31 TEMPDIODEn GNDA_PLL7 GNDA_PLL5 GNDA_PLL11 GNDA_PLL7 GNDA_PLL10 GNDA_PLL10 TEMPDIODEp GNDA_PLL5 GNDA_PLL11 7-26 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 73 Table 7-5. FPGA Pins Sorted by Bank/Signal Name (Continued) Configuration Bank Pin Type Name Other Pin Information Function Ball Board Net GNDA_PLL4 GNDA_PLL1 GNDA_PLL1 GNDA_PLL4 GNDA_PLL2 GNDA_PLL2 GNDA_PLL3 AT91CAP9A-DK Development Kit User Guide 7-27 6321B–CAP–02-Jul-07...
  • Page 74 VCCA_PLL5 VCCA_PLL VCCA_PLL11 VCCA_PLL VCCA_PLL7 VCCA_PLL VCCA_PLL10 VCCA_PLL VCCA_PLL4 VCCA_PLL VCCA_PLL1 VCCA_PLL VCCA_PLL3 VCCA_PLL VCCA_PLL2 VCCA_PLL VCCD_PLL6 AD15 VCCD_PLL VCCD_PLL12 AE18 VCCD_PLL VCCD_PLL9 VCCD_PLL VCCD_PLL8 AF25 VCCD_PLL VCCD_PLL5 VCCD_PLL VCCD_PLL7 VCCD_PLL VCCD_PLL10 VCCD_PLL 7-28 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 75 VCCIO_5 VCCIO5 VCCIO_5 VCCIO5 VCCIO_5 VCCIO6 VCCIO_6 VCCIO6 VCCIO_6 VCCIO6 VCCIO_6 VCCIO6 VCCIO_6 VCCIO7 AA16 VCCIO_7 VCCIO7 AH12 VCCIO_7 VCCIO7 AM15 VCCIO_7 VCCIO7 VCCIO_7 VCCIO8 AA17 VCCIO_8 VCCIO8 AH21 VCCIO_8 VCCIO8 AM18 VCCIO_8 AT91CAP9A-DK Development Kit User Guide 7-29 6321B–CAP–02-Jul-07...
  • Page 76 DIFFIO_RX22n FPGA29 CLK3n INPUT FPGA3 DIFFIO_TX22p FPGA30 DIFFIO_TX22n FPGA31 DIFFIO_RX21p AB30 FPGA32 DIFFIO_RX21n AB29 FPGA33 DIFFIO_TX21p FPGA34 DIFFIO_TX21n FPGA35 DIFFIO_RX20p AC32 FPGA36 DIFFIO_RX20n AC31 FPGA37 DIFFIO_TX20p AA27 FPGA38 DIFFIO_TX20n AA26 FPGA39 DIFFIO_RX28p FPGA4 7-30 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 77 FPGA62 DIFFIO_TX14n AA24 FPGA63 DIFFIO_RX13p AD30 FPGA64 DIFFIO_RX13n AD29 FPGA65 DIFFIO_TX13p AB26 FPGA66 DIFFIO_TX13n AB25 FPGA67 DIFFIO_RX12p AH32 FPGA68 DIFFIO_RX12n AH31 FPGA69 DIFFIO_TX28n FPGA7 DIFFIO_TX12p AA23 FPGA70 DIFFIO_TX12n AA22 FPGA71 DIFFIO_RX11p AE30 FPGA72 AT91CAP9A-DK Development Kit User Guide 7-31 6321B–CAP–02-Jul-07...
  • Page 78 VREFB1N1 AD28 VREFB1 VREFB1N2 VREFB1N2 AG28 VREFB1 VREFB1N0 VREFB1N0 VREFB1 PLL6_OUT1p AJ15 UGRID14 PLL6_OUT1n AH15 UGRID15 PLL6_OUT0p AK16 UGRID16 PLL6_OUT0n AJ16 UGRID17 PLL6_FBp/OUT2p AL15 UGRID18 PLL6_FBn/OUT2n AK15 UGRID19 VCC_PLL6_OUT AF15 VCC_PLL6 PLL11_OUT0p UGRID69 7-32 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 79 FPGA106 DIFFIO_TX49n FPGA107 DIFFIO_RX48p FPGA108 DIFFIO_RX48n FPGA109 DIFFIO_TX48p FPGA110 DIFFIO_TX48n FPGA111 DIFFIO_RX47p FPGA112 DIFFIO_RX47n FPGA113 DIFFIO_TX47p FPGA114 DIFFIO_TX47n FPGA115 DIFFIO_RX46p FPGA116 DIFFIO_RX46n FPGA117 DIFFIO_TX46p FPGA118 DIFFIO_TX46n FPGA119 DIFFIO_RX45p FPGA120 DIFFIO_RX45n FPGA121 DIFFIO_TX45p FPGA122 AT91CAP9A-DK Development Kit User Guide 7-33 6321B–CAP–02-Jul-07...
  • Page 80 FPGA142 DIFFIO_TX40n FPGA143 DIFFIO_RX39p FPGA144 DIFFIO_RX39n FPGA145 DIFFIO_TX39p FPGA146 DIFFIO_TX39n FPGA147 DIFFIO_RX38p FPGA148 DIFFIO_RX38n FPGA149 DIFFIO_TX38p FPGA150 DIFFIO_TX38n FPGA151 DIFFIO_RX37p FPGA152 DIFFIO_RX37n FPGA153 DIFFIO_TX37p FPGA154 DIFFIO_TX37n FPGA155 DIFFIO_RX36p FPGA156 DIFFIO_RX36n FPGA157 DIFFIO_TX36p FPGA158 7-34 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 81 DIFFIO_RX30p FPGA180 DIFFIO_RX30n FPGA181 DIFFIO_TX30p FPGA182 DIFFIO_TX30n FPGA183 DIFFIO_RX29p FPGA184 DIFFIO_RX29n FPGA185 DIFFIO_TX29p FPGA186 DIFFIO_TX29n FPGA187 CLK0n/DIFFIO_RX_C0n FPGA188 CLK0p/DIFFIO_RX_C0p FPGA189 CLK1n INPUT FPGA190 DIFFIO_TX32n FPGA191 FPLL7CLKp INPUT FPGA96 FPLL7CLKn INPUT FPGA97 DIFFIO_TX51p FPGA98 AT91CAP9A-DK Development Kit User Guide 7-35 6321B–CAP–02-Jul-07...
  • Page 82 FPGA200 DATA1 FPGA201 DQS10T FPGA202 DQ10T FPGA203 DQ10T FPGA204 DQ10T FPGA205 DQSn10T FPGA206 DQ10T FPGA207 FPGA208 FPGA209 FPGA210 FPGA211 DQS11T FPGA212 DQ11T FPGA213 DQ11T FPGA214 DQ11T FPGA215 DQSn11T FPGA216 DQ11T FPGA217 FPGA218 FPGA219 7-36 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 83 FPGA238 DQ14T FPGA239 DQ14T FPGA240 DQ14T FPGA241 DQSn14T FPGA242 DQ14T FPGA243 FPGA244 DQS15T FPGA245 DQ15T FPGA246 DQ15T FPGA247 DQ15T FPGA248 DQSn15T FPGA249 DQ15T FPGA250 FPGA251 DQS16T FPGA252 DQ16T FPGA253 DQ16T FPGA254 DQ16T FPGA255 AT91CAP9A-DK Development Kit User Guide 7-37 6321B–CAP–02-Jul-07...
  • Page 84 INIT_DONE UGRID75 VREFB3N0 VREFB3N0 VREFB3 VREFB3N2 VREFB3N2 VREFB3 VREFB3N1 VREFB3N1 VREFB3 MSEL0 MSEL0 MSEL0 MSEL1 MSEL1 MSEL1 MSEL2 MSEL2 MSEL2 MSEL3 MSEL3 MSEL3 CLK13p PISMO_AUX12 DQ0T PISMO_DM_DA0 DQ0T PISMO_DM_DA1 DQ0T PISMO_DM_DA2 DQ0T PISMO_DM_DA3 7-38 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 85 PISMO_DM_DC4 DQ5T PISMO_DM_DC5 DQ5T PISMO_DM_DC6 DQ5T PISMO_DM_DC7 DQ6T PISMO_DM_DD0 DQ6T PISMO_DM_DD1 DQ6T PISMO_DM_DD2 DQ6T PISMO_DM_DD3 DQS7T PISMO_DM_DD4 DQ7T PISMO_DM_DD5 DQ7T PISMO_DM_DD6 DQ7T PISMO_DM_DD7 PISMO_DM_DQSA_ DQS0T PISMO_DM_DQSA_ DQSn0T PISMO_DM_DQSB_ DQS2T PISMO_DM_DQSB_ DQSn2T PISMO_DM_DQSC_ DQS4T AT91CAP9A-DK Development Kit User Guide 7-39 6321B–CAP–02-Jul-07...
  • Page 86 PISMO_DM19 RUP4 PISMO_DM2 DQ5T PISMO_DM20 PISMO_DM21 PISMO_DM22 PISMO_DM23 DQSn7T PISMO_DM24 DQ7T PISMO_DM25 PISMO_DM26 DQS8T PISMO_DM27 DQ8T PISMO_DM28 DQ8T PISMO_DM29 RDN4 PISMO_DM3 DQ8T PISMO_DM30 DQSn8T PISMO_DM31 DQ8T PISMO_DM32 PISMO_DM33 PISMO_DM34 DQS9T PISMO_DM35 DQ9T PISMO_DM36 7-40 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 87 CLK11n INPUT EXT_CLK DIFFIO_TX66n PISMO_AUX10 DIFFIO_TX66p PISMO_AUX11 DIFFIO_TX67p PISMO_AUX7 DIFFIO_RX67n PISMO_AUX8 DIFFIO_RX67p PISMO_AUX9 CLK10p/DIFFIO_RX_C3p PISMO_SM0 CLK10n/DIFFIO_RX_C3n PISMO_SM1 DIFFIO_TX86n PISMO_SM10 DIFFIO_TX86p PISMO_SM11 DIFFIO_RX86n PISMO_SM12 DIFFIO_RX86p PISMO_SM13 DIFFIO_TX85n PISMO_SM14 DIFFIO_TX85p PISMO_SM15 DIFFIO_RX85n PISMO_SM16 DIFFIO_RX85p PISMO_SM17 AT91CAP9A-DK Development Kit User Guide 7-41 6321B–CAP–02-Jul-07...
  • Page 88 PISMO_SM35 DIFFIO_RX80n PISMO_SM36 DIFFIO_RX80p PISMO_SM37 DIFFIO_TX79n PISMO_SM38 DIFFIO_TX79p PISMO_SM39 DIFFIO_RX88n PISMO_SM4 DIFFIO_RX79n PISMO_SM40 DIFFIO_RX79p PISMO_SM41 DIFFIO_TX78n PISMO_SM42 DIFFIO_TX78p PISMO_SM43 DIFFIO_RX78n PISMO_SM44 DIFFIO_RX78p PISMO_SM45 DIFFIO_TX77n PISMO_SM46 DIFFIO_TX77p PISMO_SM47 DIFFIO_RX77n PISMO_SM48 DIFFIO_RX77p PISMO_SM49 DIFFIO_RX88p PISMO_SM5 7-42 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 89 PISMO_SM68 DIFFIO_RX72p PISMO_SM69 DIFFIO_TX87p PISMO_SM7 DIFFIO_TX71n PISMO_SM70 DIFFIO_TX71p PISMO_SM71 DIFFIO_RX71n PISMO_SM72 DIFFIO_RX71p PISMO_SM73 DIFFIO_TX70n PISMO_SM74 DIFFIO_TX70p PISMO_SM75 DIFFIO_RX70n PISMO_SM76 DIFFIO_RX70p PISMO_SM77 DIFFIO_TX69n PISMO_SM78 DIFFIO_TX69p PISMO_SM79 DIFFIO_RX87n PISMO_SM8 DIFFIO_RX69n PISMO_SM80 DIFFIO_RX69p PISMO_SM81 DIFFIO_TX68n PISMO_SM82 AT91CAP9A-DK Development Kit User Guide 7-43 6321B–CAP–02-Jul-07...
  • Page 90 DIFFIO_TX108n PISMO_NA10 DIFFIO_TX108p PISMO_NA11 DIFFIO_RX108n PISMO_NA12 DIFFIO_RX108p PISMO_NA13 DIFFIO_TX107n PISMO_NA14 DIFFIO_TX107p PISMO_NA15 DIFFIO_RX107n PISMO_NA16 DIFFIO_RX107p PISMO_NA17 DIFFIO_TX106n PISMO_NA18 DIFFIO_TX106p PISMO_NA19 DIFFIO_TX110n PISMO_NA2 DIFFIO_RX106n PISMO_NA20 DIFFIO_RX106p PISMO_NA21 DIFFIO_TX105n AB10 PISMO_NA22 DIFFIO_TX105p PISMO_NA23 DIFFIO_RX105n PISMO_NA24 7-44 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 91 SODIMM_S2 DIFFIO_RX102p SODIMM_S3 DIFFIO_TX101n SODIMM_S4 DIFFIO_TX101p SODIMM_S5 DIFFIO_RX101n SODIMM_S6 DIFFIO_RX101p SODIMM_S7 DIFFIO_TX100n SODIMM_S8 DIFFIO_TX100p SODIMM_S9 FPLL9CLKp INPUT UGRID20 FPLL9CLKn INPUT UGRID21 DIFFIO_RX98p UGRID22 DIFFIO_TX97n UGRID23 DIFFIO_TX97p UGRID24 DIFFIO_RX97n UGRID25 DIFFIO_RX97p UGRID26 DIFFIO_TX96n UGRID27 AT91CAP9A-DK Development Kit User Guide 7-45 6321B–CAP–02-Jul-07...
  • Page 92 DIFFIO_RX91n UGRID49 DIFFIO_RX91p UGRID50 DIFFIO_TX90n UGRID51 DIFFIO_TX90p UGRID52 DIFFIO_RX90n UGRID53 DIFFIO_RX90p UGRID54 DIFFIO_TX89n UGRID55 DIFFIO_TX89p UGRID56 DIFFIO_RX89n UGRID57 DIFFIO_RX89p UGRID58 CLK9n INPUT UGRID59 CLK9p INPUT UGRID60 CLK8n/DIFFIO_RX_C2n UGRID61 CLK8p/DIFFIO_RX_C2p UGRID62 VREFB6N1 VREFB6N1 VREFB6 7-46 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 93 SODIMM_C22 DQS6B AK10 SODIMM_C23 AD13 SODIMM_C24 AE13 SODIMM_C25 DQ5B AG12 SODIMM_C26 DQS5B AF11 SODIMM_C27 AB14 SODIMM_C28 DQSn4B SODIMM_C29 DQ9B AM14 SODIMM_C3 DQS4B SODIMM_C30 AC13 SODIMM_C31 AE12 SODIMM_C32 DQ3B SODIMM_C33 DQS3B SODIMM_C34 AB13 SODIMM_C35 AT91CAP9A-DK Development Kit User Guide 7-47 6321B–CAP–02-Jul-07...
  • Page 94 AK13 SODIMM_C8 AD14 SODIMM_C9 DQSn7B AL12 SODIMM_D0 DQ7B AM11 SODIMM_D1 DQ5B AG10 SODIMM_D10 DQ5B AF12 SODIMM_D11 DQ4B SODIMM_D12 DQ4B SODIMM_D13 DQ4B SODIMM_D14 DQ4B AJ10 SODIMM_D15 DQSn3B SODIMM_D16 DQ3B SODIMM_D17 DQ3B SODIMM_D18 DQ3B SODIMM_D19 7-48 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 95 VREFB7 VREFB7N2 VREFB7N2 VREFB7 AG25 MPIOA0 AB21 MPIOA1 DQS17B AK28 MPIOA10 AC21 MPIOA11 AG21 MPIOA12 DQ16B AK27 MPIOA13 DQSn16B AL28 MPIOA14 DQ16B AJ27 MPIOA15 DQ16B AM28 MPIOA16 DQ16B AM27 MPIOA17 DQS16B AL27 MPIOA18 AT91CAP9A-DK Development Kit User Guide 7-49 6321B–CAP–02-Jul-07...
  • Page 96 DQS13B AL23 MPIOB10 AD20 MPIOB11 DQ12B AG23 MPIOB12 DQSn12B AH22 MPIOB13 DQ12B AG22 MPIOB14 DQ12B AK22 MPIOB15 DQ12B AJ23 MPIOB16 DQS12B AJ22 MPIOB17 AC20 MPIOB18 AB19 MPIOB19 AE21 MPIOB2 AE20 MPIOB20 AC19 MPIOB21 7-50 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 97 MPIOB44 DQ13B AM24 MPIOB5 DQSn13B AL24 MPIOB6 DQ13B AK24 MPIOB7 DQ13B AK23 MPIOB8 DQ13B AM23 MPIOB9 nCONFIG nCONFIG AL30 NCONFIG CLK5p AK17 NRST AF24 S2_TCK AL31 S2_TDI AE24 S2_TMS TRST TRST AK30 TRST AT91CAP9A-DK Development Kit User Guide 7-51 6321B–CAP–02-Jul-07...
  • Page 98 Table 7-6. FPGA Pins Sorted by Signal Name Configuration Bank Pin Type Name Other Pin Information Function Ball Board Net VCCINT AA12 VCCINT AC10 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT 7-52 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 99 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCPD7 AA13 VCCPD7 AA15 VCCPD8 AA18 VCCPD8 AA20 VCCPD4 VCCPD4 VCCPD3 VCCPD3 VCCPD5 VCCPD2 AT91CAP9A-DK Development Kit User Guide 7-53 6321B–CAP–02-Jul-07...
  • Page 100 DIFFIO_TX49p FPGA106 DIFFIO_TX49n FPGA107 DIFFIO_RX48p FPGA108 DIFFIO_RX48n FPGA109 DIFFIO_TX27n FPGA11 DIFFIO_TX48p FPGA110 DIFFIO_TX48n FPGA111 DIFFIO_RX47p FPGA112 DIFFIO_RX47n FPGA113 DIFFIO_TX47p FPGA114 DIFFIO_TX47n FPGA115 DIFFIO_RX46p FPGA116 DIFFIO_RX46n FPGA117 DIFFIO_TX46p FPGA118 DIFFIO_TX46n FPGA119 DIFFIO_RX26p AA32 FPGA12 7-54 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 101 FPGA138 DIFFIO_TX41n FPGA139 DIFFIO_TX26p FPGA14 DIFFIO_RX40p FPGA140 DIFFIO_RX40n FPGA141 DIFFIO_TX40p FPGA142 DIFFIO_TX40n FPGA143 DIFFIO_RX39p FPGA144 DIFFIO_RX39n FPGA145 DIFFIO_TX39p FPGA146 DIFFIO_TX39n FPGA147 DIFFIO_RX38p FPGA148 DIFFIO_RX38n FPGA149 DIFFIO_TX26n FPGA15 DIFFIO_TX38p FPGA150 DIFFIO_TX38n FPGA151 DIFFIO_RX37p FPGA152 AT91CAP9A-DK Development Kit User Guide 7-55 6321B–CAP–02-Jul-07...
  • Page 102 DIFFIO_TX33n FPGA171 DIFFIO_RX32p FPGA172 DIFFIO_RX32n FPGA173 DIFFIO_TX32p FPGA174 CLK1p INPUT FPGA175 DIFFIO_RX31p FPGA176 DIFFIO_RX31n FPGA177 DIFFIO_TX31p FPGA178 DIFFIO_TX31n FPGA179 DIFFIO_TX25p FPGA18 DIFFIO_RX30p FPGA180 DIFFIO_RX30n FPGA181 DIFFIO_TX30p FPGA182 DIFFIO_TX30n FPGA183 DIFFIO_RX29p FPGA184 DIFFIO_RX29n FPGA185 7-56 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 103 DATA1 FPGA201 DQS10T FPGA202 DQ10T FPGA203 DQ10T FPGA204 DQ10T FPGA205 DQSn10T FPGA206 DQ10T FPGA207 FPGA208 FPGA209 DIFFIO_RX24n AB31 FPGA21 FPGA210 FPGA211 DQS11T FPGA212 DQ11T FPGA213 DQ11T FPGA214 DQ11T FPGA215 DQSn11T FPGA216 DQ11T FPGA217 AT91CAP9A-DK Development Kit User Guide 7-57 6321B–CAP–02-Jul-07...
  • Page 104 FPGA234 FPGA235 FPGA236 FPGA237 DQS14T FPGA238 DQ14T FPGA239 DIFFIO_RX23p AA30 FPGA24 DQ14T FPGA240 DQ14T FPGA241 DQSn14T FPGA242 DQ14T FPGA243 FPGA244 DQS15T FPGA245 DQ15T FPGA246 DQ15T FPGA247 DQ15T FPGA248 DQSn15T FPGA249 DIFFIO_RX23n AA29 FPGA25 7-58 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 105 DIFFIO_TX23n FPGA27 DATA3 FPGA270 DATA4 FPGA271 DATA5 FPGA272 DATA6 FPGA273 DATA7 FPGA274 RDYnBSY FPGA275 DIFFIO_RX22p FPGA28 DIFFIO_RX22n FPGA29 CLK3n INPUT FPGA3 DIFFIO_TX22p FPGA30 DIFFIO_TX22n FPGA31 DIFFIO_RX21p AB30 FPGA32 DIFFIO_RX21n AB29 FPGA33 DIFFIO_TX21p FPGA34 AT91CAP9A-DK Development Kit User Guide 7-59 6321B–CAP–02-Jul-07...
  • Page 106 DIFFIO_RX15n AG31 FPGA57 DIFFIO_TX15p FPGA58 DIFFIO_TX15n FPGA59 DIFFIO_TX28p FPGA6 DIFFIO_RX14p AC30 FPGA60 DIFFIO_RX14n AC29 FPGA61 DIFFIO_TX14p AA25 FPGA62 DIFFIO_TX14n AA24 FPGA63 DIFFIO_RX13p AD30 FPGA64 DIFFIO_RX13n AD29 FPGA65 DIFFIO_TX13p AB26 FPGA66 DIFFIO_TX13n AB25 FPGA67 7-60 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 107 FPGA89 DIFFIO_RX27n FPGA9 DIFFIO_TX7p AE28 FPGA90 DIFFIO_TX7n AE27 FPGA91 DIFFIO_RX6p AF28 FPGA92 DIFFIO_RX6n AF27 FPGA93 FPLL8CLKn INPUT AJ29 FPGA94 FPLL8CLKp INPUT AJ30 FPGA95 FPLL7CLKp INPUT FPGA96 FPLL7CLKn INPUT FPGA97 DIFFIO_TX51p FPGA98 DIFFIO_TX51n FPGA99 AT91CAP9A-DK Development Kit User Guide 7-61 6321B–CAP–02-Jul-07...
  • Page 108 Function Ball Board Net AA14 AA19 AA21 AB22 AC28 GNDA_PLL6 AD16 GNDA_PLL12 AD17 GNDA_PLL6 AE16 GNDA_PLL12 AE17 AF17 GNDA_PLL9 GNDA_PLL8 AG26 GNDA_PLL8 AG27 GNDA_PLL9 AH10 AH23 AH27 AL32 AM13 AM20 AM31 TEMPDIODEn GNDA_PLL7 7-62 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 109 Table 7-6. FPGA Pins Sorted by Signal Name (Continued) Configuration Bank Pin Type Name Other Pin Information Function Ball Board Net GNDA_PLL5 GNDA_PLL11 GNDA_PLL7 GNDA_PLL10 GNDA_PLL10 TEMPDIODEp GNDA_PLL5 GNDA_PLL11 GNDA_PLL4 AT91CAP9A-DK Development Kit User Guide 7-63 6321B–CAP–02-Jul-07...
  • Page 110 Table 7-6. FPGA Pins Sorted by Signal Name (Continued) Configuration Bank Pin Type Name Other Pin Information Function Ball Board Net GNDA_PLL1 GNDA_PLL1 GNDA_PLL4 GNDA_PLL2 GNDA_PLL2 GNDA_PLL3 GNDA_PLL3 AG25 MPIOA0 AB21 MPIOA1 DQS17B AK28 MPIOA10 AC21 MPIOA11 7-64 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 111 AK29 MPIOA6 DQ17B AJ28 MPIOA7 DQ17B AM29 MPIOA8 DQ17B AL29 MPIOA9 DQS14B AJ25 MPIOB0 AB20 MPIOB1 DQS13B AL23 MPIOB10 AD20 MPIOB11 DQ12B AG23 MPIOB12 DQSn12B AH22 MPIOB13 DQ12B AG22 MPIOB14 DQ12B AK22 MPIOB15 AT91CAP9A-DK Development Kit User Guide 7-65 6321B–CAP–02-Jul-07...
  • Page 112 AL20 MPIOB37 DQS10B AK20 MPIOB38 AC18 MPIOB39 AF20 MPIOB4 AD18 MPIOB40 AB17 MPIOB41 AC17 MPIOB42 CLK5n AJ17 MPIOB43 CLK4n AL17 MPIOB44 DQ13B AM24 MPIOB5 DQSn13B AL24 MPIOB6 DQ13B AK24 MPIOB7 DQ13B AK23 MPIOB8 7-66 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 113 PISMO_AUX4 DIFFIO_RX103n PISMO_AUX5 DIFFIO_RX103p PISMO_AUX6 DIFFIO_TX67p PISMO_AUX7 DIFFIO_RX67n PISMO_AUX8 DIFFIO_RX67p PISMO_AUX9 DQ0T PISMO_DM_DA0 DQ0T PISMO_DM_DA1 DQ0T PISMO_DM_DA2 DQ0T PISMO_DM_DA3 DQ1T PISMO_DM_DA4 DQ1T PISMO_DM_DA5 DQ1T PISMO_DM_DA6 DQSn1T PISMO_DM_DA7 DQ2T PISMO_DM_DB0 DQ2T PISMO_DM_DB1 DQ2T PISMO_DM_DB2 AT91CAP9A-DK Development Kit User Guide 7-67 6321B–CAP–02-Jul-07...
  • Page 114 PISMO_DM_DD0 DQ6T PISMO_DM_DD1 DQ6T PISMO_DM_DD2 DQ6T PISMO_DM_DD3 DQS7T PISMO_DM_DD4 DQ7T PISMO_DM_DD5 DQ7T PISMO_DM_DD6 DQ7T PISMO_DM_DD7 PISMO_DM_DQSA_ DQS0T PISMO_DM_DQSA_ DQSn0T PISMO_DM_DQSB_ DQS2T PISMO_DM_DQSB_ DQSn2T PISMO_DM_DQSC_ DQS4T PISMO_DM_DQSC_ DQSn4T PISMO_DM_DQSD_ DQS6T PISMO_DM_DQSD_ DQSn6T PISMO_DM0 PISMO_DM1 7-68 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 115 DQ7T PISMO_DM25 PISMO_DM26 DQS8T PISMO_DM27 DQ8T PISMO_DM28 DQ8T PISMO_DM29 RDN4 PISMO_DM3 DQ8T PISMO_DM30 DQSn8T PISMO_DM31 DQ8T PISMO_DM32 PISMO_DM33 PISMO_DM34 DQS9T PISMO_DM35 DQ9T PISMO_DM36 PISMO_DM4 PISMO_DM5 PISMO_DM6 PISMO_DM7 DQS1T PISMO_DM8 DQ1T PISMO_DM9 DQ9T PISMO_FS0 AT91CAP9A-DK Development Kit User Guide 7-69 6321B–CAP–02-Jul-07...
  • Page 116 DIFFIO_TX106p PISMO_NA19 DIFFIO_TX110n PISMO_NA2 DIFFIO_RX106n PISMO_NA20 DIFFIO_RX106p PISMO_NA21 DIFFIO_TX105n AB10 PISMO_NA22 DIFFIO_TX105p PISMO_NA23 DIFFIO_RX105n PISMO_NA24 DIFFIO_RX105p PISMO_NA25 DIFFIO_TX104n PISMO_NA26 DIFFIO_TX110p PISMO_NA3 DIFFIO_RX110n PISMO_NA4 DIFFIO_RX110p PISMO_NA5 DIFFIO_TX109n PISMO_NA6 DIFFIO_TX109p PISMO_NA7 DIFFIO_RX109n PISMO_NA8 DIFFIO_RX109p PISMO_NA9 7-70 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 117 PISMO_SM26 DIFFIO_TX82p PISMO_SM27 DIFFIO_RX82n PISMO_SM28 DIFFIO_RX82p PISMO_SM29 DIFFIO_TX88p PISMO_SM3 DIFFIO_TX81n PISMO_SM30 DIFFIO_TX81p PISMO_SM31 DIFFIO_RX81n PISMO_SM32 DIFFIO_RX81p PISMO_SM33 DIFFIO_TX80n PISMO_SM34 DIFFIO_TX80p PISMO_SM35 DIFFIO_RX80n PISMO_SM36 DIFFIO_RX80p PISMO_SM37 DIFFIO_TX79n PISMO_SM38 DIFFIO_TX79p PISMO_SM39 DIFFIO_RX88n PISMO_SM4 DIFFIO_RX79n PISMO_SM40 AT91CAP9A-DK Development Kit User Guide 7-71 6321B–CAP–02-Jul-07...
  • Page 118 PISMO_SM59 DIFFIO_TX87n PISMO_SM6 DIFFIO_RX74n PISMO_SM60 DIFFIO_RX74p PISMO_SM61 DIFFIO_TX73n PISMO_SM62 DIFFIO_TX73p PISMO_SM63 DIFFIO_RX73n PISMO_SM64 DIFFIO_RX73p PISMO_SM65 DIFFIO_TX72n PISMO_SM66 DIFFIO_TX72p PISMO_SM67 DIFFIO_RX72n PISMO_SM68 DIFFIO_RX72p PISMO_SM69 DIFFIO_TX87p PISMO_SM7 DIFFIO_TX71n PISMO_SM70 DIFFIO_TX71p PISMO_SM71 DIFFIO_RX71n PISMO_SM72 DIFFIO_RX71p PISMO_SM73 7-72 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 119 AB16 SODIMM_C0 AC16 SODIMM_C1 AE14 SODIMM_C10 DQ8B AG15 SODIMM_C11 DQSn8B AH14 SODIMM_C12 DQ8B AF13 SODIMM_C13 DQ8B AG13 SODIMM_C14 DQ8B AH13 SODIMM_C15 DQS8B AG14 SODIMM_C16 AB15 SODIMM_C17 AF14 SODIMM_C18 DQ7B AM12 SODIMM_C19 AC15 SODIMM_C2 AT91CAP9A-DK Development Kit User Guide 7-73 6321B–CAP–02-Jul-07...
  • Page 120 DQS1B SODIMM_C40 AD11 SODIMM_C41 AC12 SODIMM_C42 DQSn0B SODIMM_C43 AC11 SODIMM_C44 AB12 SODIMM_C45 AE10 SODIMM_C46 RDN7 AB11 SODIMM_C47 RUP7 AD10 SODIMM_C48 SODIMM_C49 DQ9B AJ13 SODIMM_C5 CLK7p AH16 SODIMM_C50 CLK7n AG16 SODIMM_C51 CLK6p AM16 SODIMM_C52 7-74 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 121 SODIMM_D24 DQ1B SODIMM_D25 DQ1B SODIMM_D26 DQ1B SODIMM_D27 DQ0B SODIMM_D28 DQ0B SODIMM_D29 DQ7B AK12 SODIMM_D3 DQ0B SODIMM_D30 DQ0B SODIMM_D31 DQ6B AM10 SODIMM_D4 DQ6B AL10 SODIMM_D5 DQ6B AH11 SODIMM_D6 DQ6B AJ11 SODIMM_D7 DQSn5B AG11 SODIMM_D8 AT91CAP9A-DK Development Kit User Guide 7-75 6321B–CAP–02-Jul-07...
  • Page 122 UGRID1 PLL12_OUT1n AH18 UGRID10 PLL12_OUT1p AJ18 UGRID11 PLL12_OUT0n AK18 UGRID12 PLL12_OUT0p AL18 UGRID13 PLL6_OUT1p AJ15 UGRID14 PLL6_OUT1n AH15 UGRID15 PLL6_OUT0p AK16 UGRID16 PLL6_OUT0n AJ16 UGRID17 PLL6_FBp/OUT2p AL15 UGRID18 PLL6_FBn/OUT2n AK15 UGRID19 AE23 UGRID2 7-76 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 123 UGRID39 RUnLU AG17 UGRID4 DIFFIO_TX93p UGRID40 DIFFIO_RX93n UGRID41 DIFFIO_RX93p UGRID42 DIFFIO_TX92n UGRID43 DIFFIO_TX92p UGRID44 DIFFIO_RX92n UGRID45 DIFFIO_RX92p UGRID46 DIFFIO_TX91n UGRID47 DIFFIO_TX91p UGRID48 DIFFIO_RX91n UGRID49 DEV_OE AH17 UGRID5 DIFFIO_RX91p UGRID50 DIFFIO_TX90n UGRID51 DIFFIO_TX90p UGRID52 AT91CAP9A-DK Development Kit User Guide 7-77 6321B–CAP–02-Jul-07...
  • Page 124 PLL11_FBn/OUT2n UGRID74 INIT_DONE UGRID75 PLL12_FBn/OUT2n AL19 UGRID8 PLL12_FBp/OUT2p AM19 UGRID9 VCC_PLL11_OUT VCC_PLL11 VCC_PLL12_OUT AF16 VCC_PLL12 VCC_PLL5_OUT VCC_PLL5 VCC_PLL6_OUT AF15 VCC_PLL6 VCCA_PLL6 AE15 VCCA_PLL VCCA_PLL9 VCCA_PLL VCCA_PLL12 AF18 VCCA_PLL VCCA_PLL8 AF26 VCCA_PLL VCCA_PLL5 VCCA_PLL 7-78 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 125 VCCIO1 AK32 VCCIO_1 VCCIO1 VCCIO_1 VCCIO1 VCCIO_1 VCCIO2 VCCIO_2 VCCIO2 VCCIO_2 VCCIO2 VCCIO_2 VCCIO2 VCCIO_2 VCCIO3 VCCIO_3 VCCIO3 VCCIO_3 VCCIO3 VCCIO_3 VCCIO3 VCCIO_3 VCCIO4 VCCIO_4 VCCIO4 VCCIO_4 VCCIO4 VCCIO_4 VCCIO4 VCCIO_4 VCCIO5 VCCIO_5 AT91CAP9A-DK Development Kit User Guide 7-79 6321B–CAP–02-Jul-07...
  • Page 126 VREFB4N2 VREFB4 VREFB4N0 VREFB4N0 VREFB4 VREFB4N1 VREFB4N1 VREFB4 VREFB5N2 VREFB5N2 VREFB5 VREFB5N1 VREFB5N1 VREFB5 VREFB5N0 VREFB5N0 VREFB5 VREFB6N1 VREFB6N1 VREFB6 VREFB6N0 VREFB6N0 VREFB6 VREFB6N2 VREFB6N2 VREFB6 VREFB7N1 VREFB7N1 VREFB7 VREFB7N0 VREFB7N0 AK14 VREFB7 7-80 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 127 Table 7-6. FPGA Pins Sorted by Signal Name (Continued) Configuration Bank Pin Type Name Other Pin Information Function Ball Board Net VREFB7N2 VREFB7N2 VREFB7 VREFB8N1 VREFB8N1 AJ24 VREFB8 VREFB8N2 VREFB8N2 AK19 VREFB8 VREFB8N0 VREFB8N0 AK31 VREFB8 CLK11p INPUT XTAL_CLK AT91CAP9A-DK Development Kit User Guide 7-81 6321B–CAP–02-Jul-07...
  • Page 128 7-82 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 129 J14 - VDDBU current measurement jumper measurement jumper Upper pin = CAP chip VDDIOM inputs Left pin = CAP chip VDDBU inputs Lower pin = board regulated VDDIOM voltage Right pin = board regulated voltage AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 130 “AT91CAP9A-DKZ Schematics” 3. Refer to to see the span of this IO bank. By default this voltage is fixed at 3.3V. Change this setting only if you are sure of what you are doing...! AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 131 AT91CAP 1.8V Memory Extension Board (AT91CAP-MEM18). Figure 9-1. AT91CAP-MEM18 Overview Memory Extension CAP Mezzanine Motherboard Purpose The AT91CAP-MEM18 board provides a composite memory extension for any AT91CAP9-DK mezza- nine. Its featured devices are 1.8V powered. AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 132 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 133 Avoid touching the component pins or any other on-board metallic element. 10.2 Requirements In order to set up an AT91CAP9A-DK development system, the following items are needed: AT91CAP9A-DKZ mezzanine board Memory extension board such as the AT91CAP-MEM18...
  • Page 134 The AT91CAP-MEM18 memory extension is powered by the AT91CAP9A-DKZ mezzanine it is con- nected to. This is automatically configured via resistor R6. This resistor sets the output level of an adjustable voltage regulator located on the mezzanine. 10-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 135 Flash device. This may be useful in case of corrupted contents, in order to force the system to boot on another default device (refer to AT91CAP9 chip and mezzanine documentation in this case). AT91CAP9A-DK Development Kit User Guide 11-1 6321B–CAP–02-Jul-07...
  • Page 136 11-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 137 AT91CAP 3.3V Memory Extension Board (AT91CAP-MEM33). Figure 12-1. AT91CAP-MEM33 Overview Memory Extension CAP Mezzanine Motherboard 12.2 Purpose The AT91CAP-MEM33 board provides a composite memory extension for any AT91CAP9-DK mezza- nine. Its featured devices are 3.3V powered. AT91CAP9A-DK Development Kit User Guide 12-1 6321B–CAP–02-Jul-07...
  • Page 138 12-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 139 Avoid touching the component pins or any other on-board metallic element. 13.2 Requirements In order to set up an AT91CAP9A-DK development system, the following items are needed: AT91CAP9A-DKZ mezzanine board Memory extension board such as the AT91CAP-MEM33...
  • Page 140 The AT91CAP-MEM33 memory extension is powered by the AT91CAP9A-DKZ mezzanine it is con- nected to. This is automatically configured via resistor R6. This resistor sets the output level of an adjustable voltage regulator located on the mezzanine. 13-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 141 Flash device. This may be useful in case of corrupted contents, in order to force the system to boot on another default device (refer to AT91CAP9 chip and mezzanine documentation in this case). AT91CAP9A-DK Development Kit User Guide 14-1 6321B–CAP–02-Jul-07...
  • Page 142 14-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 143 – USB Host Interface Serial Devices – Image Sensor Connector – SD Card/MMC Card - DataFlash Card Interface – SD Card/MMC Card Interface – Serial EEPROM Audio AC97 ADC Inputs Audio I2S LCD Panel AT91CAP9A-DK Development Kit User Guide 15-1 6321B–CAP–02-Jul-07...

  • Page 144: Mezzanine Connectors

    TP10 TP10 TP11 TP11 TP12 TP12 TP13 TP13 TP14 TP14 TP15 TP15 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 COMMUNICATION FPGA CONNECTORS DTXD DTXD DRXD DRXD FPGA[0..275] FPGA[0..275]...

  • Page 145: Power Supply

    180NF 180NF BAT20J BAT20J 2.2µH 2.2µH VIN1 VIN2 10µF 10µF SHDN LTC1765 LTC1765 C120 C120 10µF 10µF 10µF 10µF 2.2NF 2.2NF ATX POWER SUPPLY STPS2L30A STPS2L30A 180NF 180NF BAT20J BAT20J -12V 2.2µH 2.2µH VIN1 VIN2 10µF 10µF 4,99K 4,99K SHDN LTC1765 LTC1765 C121...
  • Page 146 320 pins SAMTEC SEAM-40-02.0-SM-8-2-A-K SEAM-40-02.0-SM-8-2-A-K J6-1 J6-1 J6-2 J6-2 J6-3 J6-3 J6-4 J6-4 J6-5 J6-5 J6-6 J6-6 J6-7 J6-7 J6-8 J6-8 VDDIOP1 VDDIOP1 VDDIOP1 VCCIO1 VCCIO1 NRST HDPA HDMA NRST VCCIO2 VCCIO2 HDPB HDMB HDPA HDMA VCCIO3 VCCIO3 SHDN WKUP HDPB HDMB PA10...
  • Page 147 OPTIONAL PCI POWER SUPPLY J8-1 J8-1 J8-2 J8-2 J8-3 J8-3 J8-4 J8-4 J8-5 J8-5 FPGA0 FPGA1 FPGA250 FPGA251 FPGA4 FPGA5 FPGA6 FPGA7 FPGA8 NOT POPULATED NOT POPULATED FPGA179 -12VPCI FPGA9 FPGA10 FPGA11 5VPCI 12VPCI FPGA176 FPGA[0..275] FPGA12 FPGA13 FPGA14 FPGA177 FPGA15 FPGA16 FPGA17...

  • Page 148: Upstream Interfaces

    FPGA BANK3 Powered by VCCIO3 FPGA[0..275] USB DEVICE INTERFACE VCCIO3 FPGA246 ISP1105BS ISP1105BS 1,5K 1,5K FPGA247 FPGA248 SUSPND FPGA249 SPEED FPGA2 FPGA3 33R 1% 33R 1% FPGA94 FPGA253 33R 1% 33R 1% VMO/FSE0 FPGA254 100NF 100NF VPO/VO FPGA255 SOFTCON MODE VCC5 NOT POPULATED NOT POPULATED...
  • Page 149 PA[0..31] PB[0..31] Si2301BDS Si2301BDS Si2301BDS Si2301BDS USERLED1 USERLED2 PA11 PA10 PB11 PB10 PA13 PA12 PB13 PB12 PA15 PA14 PB15 PB14 PA17 PA16 PB17 PB16 PA19 PA18 PB19 PB18 120R 120R 120R 120R PA21 PA20 PB21 PB20 PA23 PA22 PB23 PB22 PA25 PA24 PB25...
  • Page 150 EPSON EPSON SG-8002JC-50.0000M-PCB SG-8002JC-50.0000M-PCB 50 MHz 50 MHz 100NF 100NF 100NF 100NF GND_ETH TX_CLK REF_CLK/XT2 49R9 49R9 49R9 49R9 TXD3 TXD2 TXD1 TXD1 TXD0 TXD0 TX_EN TX_EN TX_CLK/ISOLATE RXD3/PHYAD3 R181 R181 AVDDT RXD2/PHYAD2 RXD1 RXD1/PHYAD1 RXD0 RXD0/PHYAD0 R182 R182 RX_CLK/10BTSER RX_DV RX_DV/TESTMODE R183...

  • Page 151: Serial Interfaces

    SERIAL DEBUG PORT 100NF 100NF 100NF 100NF MALE RIGHT ANGLE MALE RIGHT ANGLE 100NF 100NF 100NF 100NF 100NF 100NF 100K 100K DTXD DRXD ADM3202ARNZ ADM3202ARNZ D09P13A4GX00LF D09P13A4GX00LF CAN BUS CANRS CANH CANH CANTX CANL CANL 120R 120R PHOENIX CONTACT PHOENIX CONTACT CANRX MKDS 1/3-3.81 MKDS 1/3-3.81...

  • Page 152: Image Sensor Connector

    IMAGE SENSOR CONNECTOR VDDIOP1 100NF 100NF NOT POPULATED NOT POPULATED NOT POPULATED NOT POPULATED 10µF 10µF 100NF 100NF CTRL1 CTRL2 ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_D8 ISI_D9 ISI_D10 ISI_D11 SAMTEC SAMTEC TSM-115-01-L-DV TSM-115-01-L-DV ISI_D[0..11] MCI0_CD 100NF...

  • Page 153: Audio Ac97

    CLOCK SELECTION - PIN STRAPING TABLE 100µF 100µF 3.5 PHONEJACK STEREO 3.5 PHONEJACK STEREO CODEC ID CLK FREQ 742792093 742792093 PRIMARY 24.576 MHz Local XTAL SECONDARY 12.288 MHz Ext. BITCLK (see table) PRIMARY 48.000 MHz Ext. BITCLK (Into XTAL-IN) HEADPHONE AVDD_AC97 PRIMARY 14.318 MHz...

  • Page 154: Adc Inputs

    MN12C MN12C R127 R127 AD8040ARZ AD8040ARZ ADC1 R128 R128 GND_ADC MN12B MN12B R129 R129 AD8040ARZ AD8040ARZ ADC2 R130 R130 GND_ADC MN12A MN12A R131 R131 AD8040ARZ AD8040ARZ ADC3 PHOENIX CONTACT PHOENIX CONTACT MKDS 1/6-3.81 MKDS 1/6-3.81 R132 R132 GND_ADC R171 R171 NOT POPULATED NOT POPULATED GND_ADC...

  • Page 155: Audio I2S

    SYSCLK VDDD R136 R136 VDDD 100K 100K R137 R137 PCK2 100K 100K 100K 100K UDA1342TS UDA1342TS R138 R138 MN14 MN14 100NF 100NF R139 R139 R140 R140 100R 100R 3.5 PHONEJACK STEREO 3.5 PHONEJACK STEREO VDDD SYSCLK VDDD VOUTR DATAO DATAO 47 uF 47 uF VSSD...

  • Page 156: Lcd Panel

    3.5-inch 1/4 VGA TFT LCD DISPLAY MOLEX MOLEX 54132-4097 54132-4097 HITACHI HITACHI TX09D70VM1CCA TX09D70VM1CCA X_RIGHT C113 C113 R159 R159 Y_LOW 100NF 100NF NOT POPULATED NOT POPULATED X_LEFT Y_UP R160 R160 VCTRL LCD_PLATE LCD_PLATE LCDD18 LCDD19 LCDD20 R161 R161 LCDD21 LCDD22 LCDD23 B[0..5] LCDD10...
  • Page 157 15-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...

  • Page 158: This Section Contains The Following Appended Schematics

    FPGA Power 1/2 FPGA Power 2/2 FPGA I/Os FPGA I/Os Configuration – Banks 1 - 6 FPGA I/Os Configuration – Banks 7 - 8 FPGA I/Os Configuration – JTAG – AS Mode FPGA SODIMM EBI AT91CAP9A-DK Development Kit User Guide 16-1 6321B–CAP–02-Jul-07...
  • Page 159 PB[0..31] PC[0..31] RVDD_EBICAP RVDD_EBICAP TOP LEVEL VDDIOM PA[0..31] PD[0..5] PCB1 PCB1 VDDIOM VDDIOP0 VDDIOP0 PD6_NWAIT PD6_NWAIT PD7_NCS4_CFCS0 PD7_NCS4_CFCS0 PD8_NCS5_CFCS1 PD8_NCS5_CFCS1 PD9_CFCE1 PD9_CFCE1 PD9_CFCE1 PD10_CFCE2 PD10_CFCE2 PD10_CFCE2 PD11_NCS2 PD11_NCS2 PD11_NCS2 PD12_A23 PD12_A23 PD12_A23 PD13_A24 FIDU FIDU PD13_A24 PD13_A24 PD14_A25_CFRNW FD1_2007_05_04_15H00 FD1_2007_05_04_15H00 PD14_A25_CFRNW PD14_A25_CFRNW PD15_NCS3_NANDCS...
  • Page 160 FPGA user I/O - through-hole grid UGRID[0..75] UGRID0 UGRID10 UGRID20 UGRID30 UGRID40 UGRID50 UGRID60 UGRID70 UGRID1 UGRID11 UGRID21 UGRID31 UGRID41 UGRID51 UGRID61 UGRID71 UGRID2 UGRID12 UGRID22 UGRID32 UGRID42 UGRID52 UGRID62 UGRID72 UGRID3 UGRID13 UGRID23 UGRID33 UGRID43 UGRID53 UGRID63 UGRID73 UGRID4 UGRID14 UGRID24 UGRID34...
  • Page 161 Motherboard connectors SEAF_40_050_SM_8_2_A_K SEAF_40_050_SM_8_2_A_K 320 pins SAMTEC VDDIOP1 VCCIO_1 VCCIO_2 VDDIOP1 VDDIOP1 VCCIO_3 VCCIO_1 VCCIO_1 NRST HDPA HDMA VCCIO_2 VCCIO_2 HDPB NRST HDMB VCCIO_3 VCCIO_3 SHDN HDPA WKUP HDMA HDPB HDMB PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21...
  • Page 162 FPGA - PISMO connector SEAF_40_050_SM_8_2_A_K SEAF_40_050_SM_8_2_A_K 320 pins SAMTEC PISMO_DM_DQSD_DH PISMO_DM_DQSD_DL PISMO_DM27 PISMO_FS6 PISMO_FS8 PISMO_FS5 PISMO_DM_DD2 PISMO_DM_DD0 PISMO_DM18 PISMO_DM15 PISMO_DM4 PISMO_FS7 PISMO_FS4 VCCIO_4 PISMO_DM_DD3 PISMO_DM_DD1 PISMO_DM35 PISMO_DM7 PISMO_DM6 PISMO_FS3 PISMO_DM_DD5 PISMO_DM_DD4 PISMO_DM33 PISMO_DM11 PISMO_DM9 VCCIO_4 PISMO_FS2 VCCIO_5 PISMO_DM_DD6 PISMO_DM_DD7 PISMO_DM32 PISMO_DM21 PISMO_DM20 VCCIO_4...
  • Page 163 CAP - Power supply VDDCORE 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF VCCIO_8 VDDIOM VDDIOP0 VDD_PLL VCCIO_8 VDDIOM VDDIOP0 AT91CAP9 AT91CAP9 CAP9 - POWER CAP9 - POWER 100nF...
  • Page 164 CAP - Busses VDDIOM A[0..22] PA[0..31] PB[0..31] AT91CAP9 AT91CAP9 AT91CAP9 AT91CAP9 AT91CAP9 AT91CAP9 CAP9 - PIOA CAP9 - PIOA CAP9 - PIOB CAP9 - PIOB CAP9 - EBI CAP9 - EBI D[0..15] PA0/MCI0_D0/SPI0_MISO PB0/TF0 BCCLK BCCLK PA1/MCI0_CD/SPI0_MOSI PB1/TK0 CAS/BCOE PA2/MCI0_CK/SPI0_SPCK PB2/TD0 NANDOE NANDOE...
  • Page 165 CAP - USB, PLL, ICE 100k 100k 100k 100k 100k 100k 100k 100k MOLEX_0548190572 MOLEX_0548190572 VDDBU NTRST FEED = NO FEED = NO FEED = NO FEED = NO RTCK HTST_110_01_L_DV HTST_110_01_L_DV NRST ICE connector AT91CAP9 AT91CAP9 VDDBU CAP9 - SYSTEM & USB CAP9 - SYSTEM &...
  • Page 166 CAP - SODIMM EBI NRST VSS1 VSS10 DQ32 DQ33 DQ34 VDDIOP0 DQ35 VDDIOM VDDIOM VDD1 VDD10 DQ36 VDDIOM DQ37 DQ38 D[0..15] DQ39 VSS2 VSS11 PD16_D16 PD24_D24 A[0..22] DQMB0 DQMB4 PD17_D17 PD25_D25 DQMB1 DQMB5 VDDIOM VDDIOM DQS[0..1] VDD2 VDD11 PD18_D18 PD26_D26 PD19_D19 PD27_D27 NCS[0..1]...
  • Page 167 FPGA power 1/2 VCCPD ALTERA EP2S90F1020 ALTERA EP2S90F1020 Version = 1.0 Version = 1.0 VCCPD VCCINT VCCPD C197 C197 C198 C198 C199 C199 C200 C200 C201 C201 VCCPD1 VCCPD1 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF...
  • Page 168 FPGA power 2/2 C204 C204 C208 C208 C206 C206 ALTERA EP2S90F1020 ALTERA EP2S90F1020 1000uF 1000uF 1000uF 1000uF 1000uF 1000uF Version = 1.0 Version = 1.0 VREFB1 GNDA_PLL1 VREFB1N0 AD28 GNDA_PLL1 VREFB1N1 CPN = AT91RES014 CPN = AT91RES014 AG28 GNDA_PLL2 VREFB1N2 VREFB2 GNDA_PLL2 VREFB2N0...
  • Page 169 ALTERA EP2S90F1020 ALTERA EP2S90F1020 BANK 2 ALTERA EP2S90F1020 ALTERA EP2S90F1020 Version = 1.0 Version = 1.0 BANK 1 Version = 1.0 Version = 1.0 FPGA I/Os FPGA105 IO_VB2N0_E29 FPGA104 IO_VB2N0_E30 FPGA7 FPGA101 IO_VB1N0_U22 IO_VB2N0_G27 FPGA6 FPGA75 FPGA100 AB23 IO_VB1N0_U23 IO_VB1N1_AB23 IO_VB2N0_G28 FPGA11 FPGA74...
  • Page 170 FPGA I/Os, config VCCPD 220R 220R VCCSEL TP10 TP10 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 5016 HSMG-C170 HSMG-C170 nSTATUS FEED = NO FEED = NO CONFIG_DONE ALTERA EP2S90F1020 ALTERA EP2S90F1020 Version = 1.0 Version = 1.0 NRST FPGA[0..275]...
  • Page 171 FPGA I/Os, config JTAG C192 C192 EPCS64SI16N EPCS64SI16N DATA0 DATA 100nF 100nF DCLK DCLK nCSO ASDO S2_TCK ASDI S2_TDO S2_TMS VCCIO_8 S2_TDI HTST_105_01_L_DV HTST_105_01_L_DV AS Mode DCLK DS1233AZ-10 DS1233AZ-10 CONFIG_DONE nCONFIG nCONFIG nRESET DATA0 nCSO C193 C193 ASDO C220 C220 GND1 GNDTAB 100nF...
  • Page 172 FPGA - SODIMM EBI SODIMM_D[0..31] SODIMM_DQS[0..1] SODIMM_C[0..53] SODIMM_S[0..18] VSS1 VSS10 SODIMM_D0 SODIMM_D8 VCCIO_6 DQ32 SODIMM_D1 SODIMM_D9 DQ33 SODIMM_D2 SODIMM_D10 VCCIO_7 DQ34 SODIMM_D3 SODIMM_D11 DQ35 VCCIO_7 VCCIO_7 VDD1 VDD10 SODIMM_D4 SODIMM_D12 DQ36 SODIMM_D5 SODIMM_D13 DQ37 SODIMM_D6 SODIMM_D14 DQ38 SODIMM_D7 SODIMM_D15 DQ39 VSS2 VSS11 SODIMM_D16...
  • Page 173 16-2 AT91CAP9A-DK Development Kit User Guide 6321B–CAP–02-Jul-07...
  • Page 174 Section 17 AT91CAP-MEM18 Schematics 17.1 Schematics This section contains the following appended schematics: AT91CAP-MEM18 AT91CAP9A-DK Development Kit User Guide 17-1 6321B–CAP–02-Jul-07...
  • Page 175 MOBILE DDR BURST CELLULAR RAM TOP VIEW TOP VIEW FRONT FRONT REAR REAR SIDE SIDE SIDE SIDE VDDIOM VDDIOM SDA10 DQ10 DQ10 DQ11 DQ11 DQ12 DQ12 DQ13 DQ13 DQ14 DQ14 DQ15 DQ15 VDDIOM VDDIOM VDDIOM NBS0 C1 100NF C1 100NF NBS1 C2 100NF C2 100NF...
  • Page 176 Section 18 AT91CAP-MEM33 Schematics 18.1 Schematics This section contains the following appended schematics: AT91CAP-MEM33 AT91CAP9A-DK Development Kit User Guide 18-1 6321B–CAP–02-Jul-07...
  • Page 177 SDRAM MT48LC16M16A2 MT48LC16M16A2 MT48LC16M16A2 MT48LC16M16A2 TOP VIEW TOP VIEW FRONT FRONT REAR REAR SIDE SIDE SIDE SIDE SDA10 SDA10 VDDIOM VDDIOM DQ10 DQ10 DQ11 DQ11 DQ12 DQ12 DQ13 DQ13 DQ14 DQ14 DQ15 DQ15 VDDIOM VDDIOM C1 100NF C1 100NF C8 100NF C8 100NF VDDIOM VDDIOM...
  • Page 178 Section 19 Errata 19.1 Known Errata There are presently no known errata on any of the boards associated with the AT91CAP9A-DK develop- ment system. AT91CAP9A-DK Development Kit User Guide 19-1 6321B–CAP–02-Jul-07...
  • Page 179 Bank/Signal Name Table 7-6, “FPGA Pins Sorted by Signal Name Section 15 “AT91CAP-DKM Schematics” updated Section 16 “AT91CAP9A-DKZ Schematics” updated Section 17 “AT91CAP-MEM18 Schematics” updated Section 18 “AT91CAP-MEM33 Schematics” updated 6321A First issue. AT91CAP9A-DK Development Kit User Guide 20-1 6321B–CAP–02-Jul-07...
  • Page 180 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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