8-Bit Timer/Counter Register Description - Atmel AVR AT90CAN32 Manual

12.9

8-bit Timer/Counter Register Description

12.9.1 Timer/Counter0 Control Register A – TCCR0A
7679H–CAN–08/08
Figure 12-10 shows the setting of OCF0A in all modes except CTC mode.
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
clk
I/O
clk
Tn
(clk /8)
I/O
TCNTn
OCRnx
OCFnx
Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f
clk_I/O
clk
I/O
clk
Tn
(clk /8)
I/O
TCNTn
(CTC)
OCRnx
OCFnx
Bit 7
FOC0A WGM00
Read/Write W R/W
Initial Value 0
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is
the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
OCRnx - 1 OCRnx
/8)
TOP - 1
6 5 4
COM0A1 COM0A0 WGM01
R/W R/W
0 0 0
AT90CAN32/64/128
OCRnx + 1
OCRnx Value
TOP BOTTOM
TOP
3 2 1
CS02 CS01
R/W R/W R/W
0 0 0
/8)
clk_I/O
OCRnx + 2
BOTTOM + 1
0
CS00 TCCR0A
R/W
0
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