Table of Contents
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Features
®
•
Utilizes the AVR
RISC Architecture
•
High-performance and Low-power 8-bit RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
•
Nonvolatile Program and Data Memory
– 1K Byte of Flash Program Memory
™
QuickFlash
One-time Programmable (ATtiny10)
In-System Programmable (ATtiny12)
Endurance: 1,000 Write/Erase Cycles (ATtiny11/12)
– 64 Bytes of In-System Programmable EEPROM Data Memory (ATtiny12)
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– Interrupt and Wake-up on Pin Change
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
•
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port (ATtiny12)
– Enhanced Power-on Reset Circuit (ATtiny12)
– Internal Calibrated RC Oscillator (ATtiny12)
•
Specification
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.2 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
•
Packages
– 8-pin PDIP and SOIC
•
ATtiny10 is the QuickFlash OTP Version of ATtiny11
•
Operating Voltages
– 1.8 - 5.5V (ATtiny12V-1)
– 2.7 - 5.5V (ATtiny11L-2 and ATtiny12L-4)
– 4.0 - 5.5V (ATtiny11-6 and ATtiny12-8)
•
Speed Grades
– 0 - 1 MHz (ATtiny12V-1)
– 0 - 2 MHz (ATtiny11L-2)
– 0 - 4 MHz (ATtiny12L-4)
– 0 - 6 MHz (ATtiny11-6)
– 0 - 8 MHz (ATtiny12-8)
Pin Configuration
ATtiny10/11
PDIP/SOIC
(RESET) PB5
1
8
(XTAL1) PB3
2
7
(XTAL2) PB4
3
6
GND
4
5
(RESET) PB5
VCC
(XTAL1) PB3
PB2 (T0)
(XTAL2) PB4
PB1 (INT0/AIN1)
GND
PB0 (AIN0)
ATtiny12
PDIP/SOIC
1
8
VCC
2
7
PB2 (SCK/T0)
3
6
PB1 (MISO/INT0/AIN1)
4
5
PB0 (MOSI/AIN0)
8-bit
Microcontroller
with 1K Bytes
Flash
ATtiny10
ATtiny11
ATtiny12
Preliminary
Rev. 1006B–10/99
1
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Table of Contents
Related Manuals for Atmel AVR ATtiny10 Series
Summary of Contents for Atmel AVR ATtiny10 Series
- Page 1 Features ® • Utilizes the AVR RISC Architecture • High-performance and Low-power 8-bit RISC Architecture – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz •...
- Page 2 The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny10/11 is a powerful microcontroller that provides a highly-flexible and cost- effective solution to many embedded control applications.
- Page 3 ATtiny10/11/12 Figure 1. The ATtiny10/11 Block Diagram 8-BIT DATA BUS INTERNAL OSCILLATOR PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL PROGRAM HARDWARE REGISTER FLASH STACK INSTRUCTION MCU STATUS REGISTER REGISTER GENERAL- PURPOSE REGISTERS INSTRUCTION TIMER/ DECODER COUNTER CONTROL INTERRUPT LINES...
- Page 4 ATtiny12 Block Diagram Figure 2. The ATtiny12 Block Diagram 8-BIT DATA BUS INTERNAL INTERNAL CALIBRATED OSCILLATOR OSCILLATOR PROGRAM STACK WATCHDOG TIMING AND POINTER TIMER CONTROL COUNTER MCU CONTROL PROGRAM HARDWARE REGISTER FLASH STACK INSTRUCTION MCU STATUS REGISTER REGISTER GENERAL- PURPOSE REGISTERS INSTRUCTION TIMER/...
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Page 5: Pin Descriptions
The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost- effective solution to many embedded control applications. -
Page 6: Clock Options
Clock Options The device has the following clock source options, selectable by Flash fuse bits as shown: Table 3. Device Clocking Options Select Device Clocking Option ATtiny10/11 CKSEL2..0 ATtiny12 CKSEL3..0 External Crystal/Ceramic Resonator 1111 - 1010 External Low-frequency Crystal 1001 - 1000 External RC Oscillator 0111 - 0101 Internal RC Oscillator... -
Page 7: Architectural Overview
ATtiny10/11/12 External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 4. Figure 4. External Clock Drive Configuration PB4 (XTAL2) EXTERNAL XTAL1 OSCILLATOR SIGNAL External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 5 can be used. For details on how to choose R and C, see Table 29 on page 53. - Page 8 During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subroutines and interrupts. The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, timer/counters, and other I/O functions.
- Page 9 ATtiny10/11/12 General-purpose Register File Figure 7 shows the structure of the 32 general-purpose registers in the CPU. Figure 7. AVR CPU General-purpose Working Registers General- … purpose … Working Registers R30 (Z-register low byte) R31 (Z-register high byte) All the register operating instructions in the instruction set have direct- and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register and the LDI instruction for load-immediate constant data.
- Page 10 Register Direct, Single Register Rd Figure 8. Direct Single-register Addressing The operand is contained in register d (Rd). Register Indirect Figure 9. Indirect Register Addressing REGISTER FILE Z-register The register accessed is the one pointed to by the Z-register (R31, R30). ATtiny10/11/12...
- Page 11 ATtiny10/11/12 Register Direct, Two Registers Rd and Rr Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 11. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word.
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Page 12: Subroutine And Interrupt Hardware Stack
Relative Program Addressing, RJMP and RCALL Figure 12. Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Constant Addressing Using the LPM Instruction Figure 13. Code Memory Constant Addressing PROGRAM MEMORY $000 Z-REGISTER... -
Page 13: Eeprom Data Memory
ATtiny10/11/12 EEPROM Data Memory The ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 33, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register. - Page 14 I/O Memory The I/O space definition of the ATtiny10/11/12 is shown in the following table: Table 4. ATtiny10/11/12 I/O Space Address Hex Name Device Function SREG ATtiny10/11/12 Status Register GIMSK ATtiny10/11/12 General Interrupt Mask Register GIFR ATtiny10/11/12 General Interrupt Flag Register TIMSK ATtiny10/11/12 Timer/Counter Interrupt Mask Register...
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Page 15: Reset And Interrupt Handling
ATtiny10/11/12 are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. • Bit 6 - T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. - Page 16 Table 5. Reset and Interrupt Vectors Vector No. Device Program Address Source Interrupt Definition External Pin, Power-on Reset and ATtiny10/11 $000 RESET Watchdog Reset External Pin, Power-on Reset, Brown-out ATtiny12 $000 RESET Reset and Watchdog Reset ATtiny10/11/12 $001 INT0 External Interrupt Request 0 ATtiny10/11/12 $002 I/O Pins...
- Page 17 ATtiny10/11/12 Reset Sources The ATtiny10/11/12 provides three or four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. •...
- Page 18 Power-on Reset for the ATtiny10/11 A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 16, an internal timer is clocked from the watchdog timer. This timer prevents the MCU from starting a certain period after V has reached the Power-on Threshold Voltage –...
- Page 19 ATtiny10/11/12 Table 8. Reset Characteristics for the ATtiny12 Symbol Parameter Condition Units BOD disabled Power-on Reset Threshold Voltage (rising) BOD enabled BOD disabled Power-on Reset Threshold Voltage (falling) BOD enabled RESET Pin Threshold Voltage 0.6V (BODLEVEL = 1) Brown-out Reset Threshold Voltage (BODLEVEL = 0) Note: 1.
- Page 20 Table 10. Number of Watchdog Oscillator Cycles BODLEVEL Time-out Number of Cycles Unprogrammed 3.6 ms (at V = 1.8V) Unprogrammed 57 ms (at V = 1.8V) Programmed 4.2 ms (at V = 2.7V) Programmed 67 ms (at V = 2.7V) The frequency of the watchdog oscillator is voltage dependent as shown in the section “ATtiny11 Typical Characteristics”...
- Page 21 ATtiny10/11/12 Figure 19. MCU Start-up, RESET Extended Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage –...
- Page 22 Figure 21. Brown-out Reset during Operation (ATtiny12) BOT+ BOT- RESET TIME-OUT TOUT INTERNAL RESET Note: The hysteresis on V + 25 mV, V - 25 mV. BOT + BOT- Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period (t ).
- Page 23 ATtiny10/11/12 • Bit 0 - PORF: Power-on Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged. To summarize, the following table shows the value of these two bits after the three modes of reset. Table 11.
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Page 24: Interrupt Handling
Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The maximum start-up time is TBD. To save power, the reference is not always turned on. The reference is on during the following situations: 1. - Page 25 ATtiny10/11/12 cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bit 5 - PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt on pin change is enabled.
- Page 26 • Bit 1 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
- Page 27 ATtiny10/11/12 • Bits 3, 2 - Res: Reserved bits These bits are reserved bits in the ATtiny10/11/12 and always read as zero. • Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control0 bit 1 and bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
- Page 28 Sleep Modes for the ATtiny12 To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes.
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Page 29: Timer/Counter Prescaler
ATtiny10/11/12 nominal frequency. Otherwise, the EEPROM write may fail. Table 14 shows the range for OSCCAL. Note that the oscillator is intended for calibration to 1.0 MHz, thus tuning to other values is not guaranteed. Table 14. Internal RC Oscillator Frequency Range OSCCAL Value Min Frequency Max Frequency... - Page 30 The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportuni- ties. Similarly, the high-prescaling opportunities make the Timer/Counter0 useful for lower-speed functions or exact-timing functions with infrequent actions. Figure 24. Timer/Counter0 Block Diagram Timer/Counter0 Control Register – TCCR0 CS02 CS01 CS00...
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Page 31: Watchdog Timer
ATtiny10/11/12 The Stop condition provides a Timer Enable/Disable function. The CK down-divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting. Timer Counter 0 –... - Page 32 Watchdog Timer Control Register – WDTCR WDTOE WDP2 WDP1 WDP0 WDTCR Read/Write Initial value • Bits 7..5 - Res: Reserved bits These bits are reserved bits in the ATtiny10/11/12 and will always read as zero. • Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared.
- Page 33 ATtiny10/11/12 ATtiny12 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 1.9 - 3.4 ms, depending on the frequency of the calibrated RC oscillator. See Table 17 for details. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data.
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Page 34: Prevent Eeprom Corruption
• Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. -
Page 35: Analog Comparator
ATtiny10/11/12 Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Com- parator Output (ACO) is set (one). - Page 36 • Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 - Res: Reserved bit This bit is a reserved bit in the ATtiny10/11/12 and will always read as zero.
- Page 37 ATtiny10/11/12 Table 19. Port B Pins Alternate Functions (Continued) Port Pin Alternate Functions Device T0 (Timer/Counter0 External Counter Input) ATtiny10/11/12 SCK (Serial Clock Input for Serial Programming) ATtiny12 XTAL1 (Oscillator Input) ATtiny10/11/12 XTAL2 (Oscillator Output) ATtiny10/11/12 RESET (External Reset Pin) ATtiny10/11/12 When the pins PB2..0 are used for the alternate function, the DDRB and PORTB register has to be set according to the alternate function description.
- Page 38 Port B as General Digital I/O The lowermost five pins in port B have equal functionality when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin.
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Page 39: Memory Programming
ATtiny10/11/12 • AIN0/MOSI - Port B, Bit 0 This pin also serves as the positive input of the on-chip Analog Comparator. In ATtiny12 and serial programming mode, this pin serves as the serial data output, MOSI. During Power-down Mode, the schmitt triggers of the digital inputs are disconnected on the Analog Comparator input pins. This allows an analog voltage close to V /2 to be present during power-down without causing excessive power consumption. -
Page 40: Signature Bytes
Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0 and/or PB5. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. The three bytes reside in a sepa- rate address space. - Page 41 ATtiny10/11/12 ATtiny12 Atmel’s ATtiny12 offers 1K bytes of in-system reprogrammable Flash Program memory and 64 bytes of in-system repro- grammable EEPROM Data memory. The ATtiny12 is shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e.
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Page 42: High-Voltage Serial Programming
ATtiny10/11/12 During programming, the supply voltage must be in accordance with Table 22. Table 22. Supply Voltage during Programming Part Low-voltage Serial Programming High-voltage Serial Programming ATtiny10/11L Not applicable 4.5 - 5.5V ATtiny10/11 Not applicable 4.5 - 5.5V ATtiny12V 2.2 - 5.5V 4.5 - 5.5V ATtiny12L 2.7 - 5.5V... - Page 43 ATtiny10/11/12 Figure 28. High-voltage Serial Programming Waveforms SERIAL DATA INPUT SERIAL INSTR. INPUT SERIAL DATA OUTPUT SERIAL CLOCK INPUT XTAL1/PB3 Table 23. High-voltage Serial Programming Instruction Set for ATtiny10/11/12 Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.4 Operation Remarks Chip Erase 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00...
- Page 44 Table 23. High-voltage Serial Programming Instruction Set for ATtiny10/11/12 (Continued) Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.4 Operation Remarks Read EEPROM 0_0000_0000_00 0_0000_0000_00 Repeat Instr.2 for each new byte (ATtiny12) address 0_0110_1000_00 0_0110_1100_00 x_xxxx_xxxx_xx o_oooo_ooox_xx Write Fuse bits 0_0100_0000_00 0_0007_6543_00 0_0000_0000_00 0_0000_0000_00 Wait...
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Page 45: High-Voltage Serial Programming Characteristics
ATtiny10/11/12 High-voltage Serial Programming Characteristics Figure 29. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SLSH IVSH SHIX SCI (PB3) SHSL SDO (PB2) SHOV Table 24. High-voltage Serial Programming Characteristics = 25 ° C ± 10%, V = 5.0V ± 10% (Unless otherwise noted) Symbol Parameter Units... - Page 46 The device can be clocked by any clock option during Low-voltage Serial Programming . The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles Low-voltage Serial Programming Algorithm When writing serial data to the ATtiny12, data is clocked on the rising edge of SCK.
- Page 47 ATtiny10/11/12 Data Polling When a byte is being programmed into the Flash or EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
- Page 48 Table 25. Low-voltage Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Enable serial programming while 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Programming Enable RESET is low. Chip erase Flash and EEPROM 1010 1100 100x xxxx xxxx xxxx...
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Page 49: Low-Voltage Serial Programming Characteristics
ATtiny10/11/12 Low-voltage Serial Programming Characteristics Figure 32. Low-voltage Serial Programming Timing MOSI SLSH OVSH SHOX SHSL MISO SLIV Table 26. Low-voltage Serial Programming Characteristics = -40 ° C to 85 ° C, V = 2.2 - 5.5V (Unless otherwise noted) Symbol Parameter Units... - Page 50 Electrical Characteristics Absolute Maximum Ratings *NOTICE: Stresses beyond those ratings listed under Operating Temperature........-55°C to +125°C “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating Storage Temperature ........-65°C to +150°C only and functional operation of the device at Voltage on any Pin except RESET these or other conditions beyond those indicated with respect to Ground ........-1.0V to V...
- Page 51 ATtiny10/11/12 DC Characteristics – Preliminary Data = -40 ° C to 85 ° C, V = 2.7V to 5.5V for ATtiny10/11, V = 1.8V to 5.5V for ATtiny12 (Unless otherwise noted) Symbol Parameter Condition Units Input Low Voltage Except (XTAL) -0.5 0.3 V Input Low Voltage...
- Page 52 DC Characteristics – Preliminary Data (Continued) = -40 ° C to 85 ° C, V = 2.7V to 5.5V for ATtiny10/11, V = 1.8V to 5.5V for ATtiny12 (Unless otherwise noted) Symbol Parameter Condition Units Analog Comparator = 5V ACIO Input Offset Voltage Analog Comparator = 5V...
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Page 53: External Clock Drive Waveforms
ATtiny10/11/12 External Clock Drive Waveforms Figure 33. External Clock VIH1 VIL1 External Clock Drive ATtiny10/11 = 2.7V to 4.0V = 4.0V to 5.5V Symbol Parameter Units Oscillator Frequency CLCL Clock Period CLCL High Time CHCX Low Time CLCX Rise Time µs CLCH Fall Time... - Page 54 ATtiny11 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave genera- tor with rail-to-rail output is used as clock source. The power consumption in Power-down Mode is independent of clock selection.
- Page 55 ATtiny10/11/12 Figure 35. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ Figure 36. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25 ˚...
- Page 56 Figure 37. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ Figure 38. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED T = 85 ˚...
- Page 57 ATtiny10/11/12 Figure 39. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 85 T = 25 ˚ ˚ Figure 40. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V T = 25 ˚ T = 85 ˚...
- Page 58 Analog comparator offset voltage is measured as absolute offset. Figure 41. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 42.
- Page 59 ATtiny10/11/12 Figure 43. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25 ˚ V (V) Figure 44. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 T = 25 ˚ 1200 T = 85 ˚...
- Page 60 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 45. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 5V T = 25 ˚ T = 85 ˚ Figure 46. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs.
- Page 61 ATtiny10/11/12 Figure 47. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE = 5V T = 25 ˚ T = 85 ˚ Figure 48. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE = 5V T = 25 ˚...
- Page 62 Figure 49. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE = 2.7V T = 25 ˚ T = 85 ˚ Figure 50. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE = 2.7V T = 25 ˚...
- Page 63 ATtiny10/11/12 Figure 51. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ Figure 52. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12...
- Page 64 ATtiny12 Typical Characteristics – PRELIMINARY DATA The following charts show typical behavior. These data are characterized, but not tested. All current consumption measure- ments are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
- Page 65 ATtiny10/11/12 Analog Comparator offset voltage is measured as absolute offset. Figure 54. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE = 5V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 55.
- Page 66 Figure 56. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT = 6V T = 25 ˚ V (V) Figure 57. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 T = 25 ˚ 1200 T = 85 ˚...
- Page 67 ATtiny10/11/12 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 58. Pull-up Resistor Current vs. Input Voltage (V = 5V) T = 25 ˚ T = 85 ˚ Figure 59. Pull-up Resistor Current vs. Input Voltage (V = 2.7V) T = 25 ˚...
- Page 68 Figure 60. I/O Pin Sink Current vs. Output Voltage (V = 5V) T = 25 ˚ T = 85 ˚ Figure 61. I/O Pin Source Current vs. Output Voltage (V = 5V) T = 25 ˚ T = 85 ˚ ATtiny10/11/12...
- Page 69 ATtiny10/11/12 Figure 62. I/O Pin Sink Current vs. Output Voltage (V = 2.7V) T = 25 ˚ T = 85 ˚ Figure 63. I/O Pin Source Current vs. Output Voltage (V = 2.7V) T = 25 ˚ T = 85 ˚...
- Page 70 = 25 ° C) Figure 64. I/O Pin Input Threshold Voltage vs. V = 25 ° C) Figure 65. I/O Pin Input Hysteresis vs. V 0.18 0.16 0.14 0.12 0.08 0.06 0.04 0.02 ATtiny10/11/12...
- Page 71 ATtiny10/11/12 Register Summary ATtiny10/11 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page SREG page 14 Reserved Reserved Reserved GIMSK INT0 PCIE page 24 GIFR INTF0 PCIF page 25 TIMSK TOIE0 page 25 TIFR...
- Page 72 Register Summary ATtiny12 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page SREG page 14 Reserved Reserved Reserved GIMSK INT0 PCIE page 24 GIFR INTF0 PCIF page 25 TIMSK TOIE0 page 25 TIFR TOV0...
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Page 73: Instruction Set Summary
ATtiny10/11/12 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ← Rd, Rr Add two Registers Rd + Rr Z,C,N,V,H ← Rd, Rr Add with Carry two Registers Rd + Rr + C Z,C,N,V,H ← Rd, Rr Subtract two Registers Rd - Rr Z,C,N,V,H... - Page 74 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks DATA TRANSFER INSTRUCTIONS ← Rd,Z Load Register Indirect None ← Z,Rr Store Register Indirect None ← Rd, Rr Move Between Registers None ← Rd, K Load Immediate None ← Rd, P In Port None ←...
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Page 75: Ordering Information
ATtiny10/11/12 Ordering Information Power Supply Speed (MHz) Ordering Code Package Operation Range 2.7 - 5.5V ATtiny11L-2PC Commercial ATtiny11L-2SC (0°C to 70°C) ATtiny11L-2PI Industrial ATtiny11L-2SI (-40°C to 85°C) 4.0 - 5.5V ATtiny11-6PC Commercial ATtiny11-6SC (0°C to 70°C) ATtiny11-6PI Industrial ATtiny11-6SI (-40°C to 85°C) 1.8 - 5.5V ATtiny12V-1PC Commercial... -
Page 76: Packaging Information
Packaging Information 8P3, 8-lead, 0.300" Wide, 8S2, 8-lead, 0.200" Wide, Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .020 (.508) .400 (10.16) .355 (9.02) .012 (.305) .213 (5.41) - Page 77 No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems.