Limitations; Power Reduction Register - Atmel ATtiny25 Manual

7.5

Limitations

7.6

Power Reduction Register

7598H–AVR–07/09
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details .
.
Table 7-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
Note: 1. For INT0, only level interrupt.
BOD disable functionality has been implemented in the following devices, only:
• ATtiny25, revision D, and newer
• ATtiny45, revision D, and newer
• ATtiny85, revision C, and newer
The Power Reduction Register, PRR, provides a method to stop the clock to individualperipher-
als to reduce power consumption. The current state of the peripheral is frozenand the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
Bit 7
–
Read/Write R
Initial Value 0
• Bits 7, 6, 5, 4- Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3- PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
Oscillators
X X X
X
6 5 4
- - -
R R R
0 0 0
ATtiny25/45/85
"External Interrupts" on page 58
Wake-up Sources
X X X
(1)
X X X
(1)
X
3 2 1
PRTIM1 PRTIM0 PRUSI
R/W R/W R/W
0 0 0
X X X X
X X X
X X
0
PRADC PRR
R/W
0
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