Timer/Counter1 Dead Time Prescaler Register 1 - Dtps1 - Atmel ATtiny25 Manual

15.1

Timer/Counter1 Dead Time Prescaler register 1 - DTPS1

ATtiny25/45/85
94
The length of the counting period is user adjustable by selecting the dead time prescaler setting
in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register
consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM
output and its' complementary output separately. Thus the rising edge of OC1x and OC1x can
have different dead time periods. The dead time is adjusted as the number of prescaled dead
time generator clock cycles.
Figure 15-3. The Complementary Output Pair
PWM1x
OC1x
OC1x
x = A or B
t
non-overlap / rising edge
Bit 7
$23 ($43)
Read/Write R
Initial value 0
The dead time prescaler register, DTPS1 is a 2-bit read/write register.
Bits 1 - 0 - DTPS1: Timer/Counter1 Dead Time Prescaler register 1
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the
Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can
be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead
Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The
division factors are given in table 46..
Table 15-1. Division factors of the Dead Time prescaler
DTPS11 DTPS10
0 0
0 1
1 0
1 1
t
non-overlap / falling edge
6 5 4
R R R
0 0 0
Prescaler divides the T/C1 clock by
1x (no division)
2x
4x
8x
3 2 1
DTPS11
R R R/W
0 0 0
0
DTPS10 DTPS1
R/W
0
7598H–AVR–07/09