Idle Mode; Adc Noise Reduction Mode; Power-Down Mode - Atmel ATtiny25 Manual

7.2

Idle Mode

7.3

ADC Noise Reduction Mode

7.4

Power-down Mode

ATtiny25/45/85
32
Table 7-1. Sleep Mode Select
SM1
0
0
1
1
• Bit 2 – BODSE: BOD Sleep Enable
BOD disable functionality is available in some devices, only. See
The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD
disable is controlled by a timed sequence.
This bit is unused in devices where software BOD disable has not been implemented and will
read as zero in those devices.
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the
ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the
Watchdog to continue operating (if enabled). This sleep mode halts clk
while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change
interrupt can wake up the MCU from ADC Noise Reduction mode.
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the
Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a
Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the
MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules
only.
SM0 Sleep Mode
0 Idle
1 ADC Noise Reduction
0 Power-down
1 Stand-by mode
"Limitations" on page 33.
and clk
CPU FLASH
, clk , and clk
I/O CPU
7598H–AVR–07/09
, while
,
FLASH