General Interrupt Flag Register - Gifr; Pin Change Mask Register - Pcmsk - Atmel ATtiny25 Manual

11.3 General Interrupt Flag Register – GIFR
11.4 Pin Change Mask Register – PCMSK
ATtiny25/45/85
60
Bit 7
–
Read/Write R
Initial Value 0
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
Bit 7
–
Read/Write R
Initial Value 0
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0
Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
6 5 4
INTF0 PCIF –
R/W R/W R
0 0 0
6 5 4
– PCINT5 PCINT4
R R/W R/W
0 1 1
3 2 1
– – –
R R R
0 0 0
3 2 1
PCINT3 PCINT2 PCINT1
R/W R/W R/W
1 1 1
0
– GIFR
R
0
0
PCINT0 PCMSK
R/W
1
7598H–AVR–07/09