Eeprom Data Memory - Atmel ATtiny25 Manual

5.2.1 Data Memory Access Times
5.3

EEPROM Data Memory

5.3.1 EEPROM Read/Write Access
7598H–AVR–07/09
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3. On-chip Data SRAM Access Cycles
clk
CPU
Address
Data
WR
Data
RD
The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For a detailed description of Serial data
downloading to the EEPROM, see
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V is likely to rise or fall slowly on Power-up/down. This causes the device for some
CC
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See "Preventing EEPROM Corruption" on page 20
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to "Atomic Byte Programming" on page 18
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
CPU
T1 T2
Address valid
Compute Address
Memory Access Instruction
page 138.
for details on how to avoid problems in these
and
ATtiny25/45/85
cycles as described in Figure
T3
Next Instruction
Table 5-1. A self-timing function, however,
"Split Byte Programming" on page 18
5-3.
for
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