Power-On Reset - Atmel ATtiny25 Manual

8.3

Power-on Reset

ATtiny25/45/85
36
Figure 8-1. Reset Logic
BODLEVEL [1..0]
Pull-up Resistor
SPIKE
FILTER
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 8-1. The POR is activated whenever V
POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V decreases below the detection level.
CC
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
Watchdog
Oscillator
Delay Counters
Clock
CK
Generator
CKSEL[1:0]
SUT[1:0]
rise. The RESET signal is activated again, without any delay,
CC
TIMEOUT
is below the detection level. The
CC
7598H–AVR–07/09