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AT40K Series Configuration
Configuration is the process by which a design is loaded into an AT40K series field
programmable gate array (FPGA). AT40K series devices are SRAM based and can be
configured any number of times. The entire device or select portions can be config-
ured. Sections can be configured while others continue to operate undisturbed. Full
configuration takes only milliseconds. Partial configuration takes even less time and is
a function of design density.
Configuration data is transferred to the device in one of six modes, see Table 1. Three
dedicated input pins, M
0
auto-configuring Master Mode, four Slave modes, and a Synchronous RAM Mode for
accessing the SRAM-based configuration memory directly from a parallel micropro-
cessor port.
Configuration States
There are four basic configuration states of operation. The first, power-on-reset,
occurs when power is first applied to the part. The FPGA initiates a complete clearing
of all internal configuration SRAM (configuration clear cycle).
The second, manual reset, occurs when the RESET pin is driven Low by the user.
Again, the FPGA initiates a configuration clear cycle.
The third is configuration download. In this state the configuration mode is active. The
FPGA accepts serial or parallel data from an outside source and configures the con-
figuration SRAM appropriately.
The fourth is idle, when there is no configuration activity.
Table 1. AT40K Series Configuration Modes
Mode
Description
0
Master Serial
1
Slave Serial
7
Slave Serial
2
Slave Parallel
6
Slave Parallel UP
4
Synchronous
RAM
, M
, and M
, determine the configuration mode. There is one
1
2
M
M
M
CCLK
2
1
0
0
0
0
Output
0
0
1
Input
1
1
1
Input
0
1
0
Input
1
1
0
Input
1
0
0
Input
Data
Notes
Serial
Auto-Configuration,
Serial EEPROM
Serial
Microprocessor or
Serial EEPROM
Serial
Microprocessor or
Serial EEPROM
8- or 16-bit
Microprocessor or
Word
Parallel EEPROM
8- or 16-bit
20-bit Address Out,
Word
Parallel EPROM
8- or 16-bit
24-bit Address In,
Word
Parallel Port of
Microprocessor
AT40K FPGA
Application
Note
Rev. 1009B–FPGA–03/02
1
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Related Manuals for Atmel AT40K
Summary of Contents for Atmel AT40K
- Page 1 AT40K Series Configuration AT40K FPGA Configuration is the process by which a design is loaded into an AT40K series field programmable gate array (FPGA). AT40K series devices are SRAM based and can be configured any number of times. The entire device or select portions can be config- ured.
-
Page 2: Master Mode
During configuration, the flow of design data to and from the device is controlled by the dedicated mode pins and a number of dual-function pins that double as user I/O under normal programmed operation. The number of dual-function pins required for each mode varies, see Table 2. AT40K Series Configuration 1009B–FPGA–03/02... - Page 3 AT40K Series Configuration Table 2. Configuration Pins Interface Definition State Download Download Download Download Download Download Pins Reset Mode 0 Mode 1 Mode 7 Mode 2 Mode 6 Mode 4 Idle TTL Input TTL Input TTL Input TTL Input TTL Input...
- Page 4 “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the user programmed state at the end of configuration download. If not pro- grammed, the default state is input with pull-up. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 5 AT40K Series Configuration LDC is the FPGA “Low During Configuration” pin. It is an output driven Low by the FPGA during power-on-reset, manual reset, and configuration download. During config- uration idle, the pin is a fully functional user I/O. Note: All user I/O pull-ups and put-downs are programmed by the user.
- Page 6 This implies that any user logic tied to the input buffers of the pins in question will remain operational, see Figure 1. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 7 From configuration Configuration States When power is first applied to an AT40K series FPGA, an internal power-on-reset circuit senses VDD and activates at approximately 2.1V. The FPGA then enters the power-on- reset state. During this state, INIT is driven Low, CON is driven Low, LDC is driven Low, HDC is driven High, and all user I/O are tri-stated.
- Page 8 Pull-up enabled Pull-down disabled Clocks Tied High Resets Tied Low (active) Disabled Contents cleared There is no activity in either the user logic or the configuration logic and the device is in a low power state. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 9 FPGA while the rest of the FPGA continues to operate unaffected. Control of the FPGA system level interface is possible on an AT40K series FPGA. User I/O, internal Global Set/Reset, and Global and Fast Clocks can be enabled or disabled during configuration downloads by setting bits in the control register.
- Page 10 INIT and RESET are inactive (High), a Mode 0 FPGA starts CCLK and configu- ration download. Configuration The AT40K series devices have a 32-bit control register that is written at the beginning of a configuration download. These bits control various configuration sequence parame- Control Register ters.
- Page 11 AT40K Series Configuration 0 = Memory Lockout disabled 1 = Memory Lockout enabled is the Security Flag and controls the writing and checking of configuration memory during any subsequent configuration download. When CR is set, any subsequent con- figuration download initiated by the user, whether a normal download or a CHECK function download, causes the INIT pin to immediately activate.
- Page 12 0 = Disable I/O tri-state 1 = I/O tri-state during configuration forces all user defined I/O pins to go tri-state during configuration download. tri-state is released at the end of configuration download on the rising edge of CON. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 13 (Figure 3). The state machine is clocked by CCLK. On the rising edge of each CCLK a bit or byte of the configuration data bitstream is clocked into the device. Figure 6 dis- plays a sample 8-bit wide bitstream for an AT40K series device. Figure 3. Configuration Download State Machine...
- Page 14 CS ) is activated, the device begins clocking data. For AT40K series devices, the timing relationships are fixed, and no additional data is allowed at the front of the bitstreams. Serial data is read in the most-significant-bit first. The null byte is read in, followed by the preamble. If the expected preamble value is not seen as the second byte of data, an error is reported by driving INIT Low and terminat- ing the configuration download.
- Page 15 At the start of any subsequent re-configuration, pins D will be claimed immediately upon CON going Low. Atmel recommends not moving between 8- and 16-bit data bandwidths. 1009B–FPGA–03/02...
-
Page 16: Check Function
Full vs. Partial In programming an AT40K series FPGA, the user will normally load the entire configura- tion SRAM memory map from start to finish. This requires a full bitstream. Bitstream Bitstreams sizes are shown in Table 8. Table 8. AT40K Series Bitstream sizes... - Page 17 AT40K Series Configuration Checksum Function The AT40K family supports a Checksum Function. During a configuration download, an accumulated checksum is calculated after each word (8- or-16 bits) of the bitstream is downloaded to the FPGA. During the bitstream download, the user may write to a series of registers in a special window known as the Checksum Page.
- Page 18 Synchronous RAM The AT40K family supports the writing and reading of design specific data to or from the FPGA configuration SRAM by means of a simple single port synchronous SRAM type Configuration interface. This interface, requires no configuration state machine during the download Downloads (Mode 4) process.
-
Page 19: User Control
AT40K Series Configuration Figure 4. System Level Integration: Start of Configuration CCLK 10K PULL-UP DCGTS (OPTIONALLY TRISTATED DURING CONFIGURATION) USER CONTROL GLOBAL SET/ RESET NET DGSR USER CONTROL (OPTIONALLY FORCED ON (LOW) DURING CONFIGURATION) GCLK ,FCLK INTERNAL CLOCK NET (OPTIONALLY DISABLED DURING CONFIGURATION) Notes: 1. - Page 20 FPGA are still inactive. This implies that no system integration problems will occur on the first download after power-on-reset or manual reset. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 21 INIT RESET In Mode 0, CCLK is driven by the Master Serial AT40K FPGA into an Atmel Configurator that drives data out its Data pin and into the D0 pin of the FPGA. Each CCLK increments the Configurator internal address counter, and serial data is presented to the FPGA.
- Page 22 Figure 7. Master Serial Start of Auto-configuration Download 50K PULL-UP (INTERNAL) PCCLK CCLK INIT ICCLK 20K PULL-UP (INTERNAL) RESET BITSTREAM BIT 0 BIT 3 BIT 2 BIT 1 20K PULL-UP (INTERNAL) Note: 1. Parameter t is taken from the AT17 series datasheet. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 23 AT40K Series Configuration Figure 8. Master Serial Start of Re-configuration (without reset) 50K PULL-UP (INTERNAL) DCCLKH CCLK DRIVEN BY USER ONLY USER MAY RELEASE 10K PULL-UP (INTERNAL) (1)(5) USER I/O INIT 20K PULL-UP (INTERNAL) SCCCLK CHECK USER I/O USER I/O...
- Page 24 Actual time will depend on system loading of CON. Delay from rising edge of CCLK to the release of dual-use pins to full user functionality. Delay from rising edge of CCLK to CSOUT active at end of configuration. DCSOUT AT40K Series Configuration 1009B–FPGA–03/02...
- Page 25 AT40K Series Configuration Mode 1: Slave Serial Configuration Data Source: Serial EEPROM, Microprocessor Dedicated Configuration Pins: RESET, CON, M CCLK Dual-use I/O: , INIT, LDC, HDC, Optional Dual-use I/O: CSOUT, CHECK, OTS Figure 10. Stand-alone 1 Microprocessor System Application IO<31>...
- Page 26 Figure 14 shows the timing of the configuration interface at the interface of the upstream and downstream devices in the cascade chain. Table 12 shows the configuration timing parameters pertaining to these timing diagrams. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 27 AT40K Series Configuration Figure 12. Slave Serial Start of Configuration PCCLK CCLK DRIVEN BY USE ONLY USER MAY RELEASE 10K PULL-UP (INTERNAL) INIT USER I/O 20K PULL-UP (INTERNAL) SCCCLK CHECK USER I/O USER I/O USER I/O USER I/O BIT 0...
- Page 28 “1”. The error is shown for timing purposes only; under normal circumstances the bitstream download would terminate prematurely. 2. The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control register. Both are enabled by default after power-on-reset or manual reset. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 29 AT40K Series Configuration Figure 14. Serial Cascade Chain Interface Timing Diagram CCLK UPSTREAM DEVICE DRIVES ONLY BOTH DRIVE DOWNSTREAM DEVICE DRIVES ONLY CSOUT(FROM UPSTREAM) CS0 (TO DOWNSTREAM) INIT 20K PULL-UP (INTERNAL) USER I/O (DOWNSTREAM DEVICE) DATA IN LAST BIT OF POSTAMBLE...
- Page 30 CCLK. The maximum frequency in which a Mode 7 device can be downloaded is 33 MHz. A full bitstream for the AT40K20 can be downloaded in only 4.6 ms (30 ns per bit of configuration data). AT40K Series Configuration 1009B–FPGA–03/02...
- Page 31 AT40K Series Configuration Figure 16. Slave Serial Start of Configuration PCCLK CCLK DRIVEN BY USE ONLY USER MAY RELEASE 10K PULL-UP (INTERNAL) USER I/O INIT 20K PULL-UP (INTERNAL) SCCCLK CHECK USER I/O USER I/O USER I/O USER I/O BIT 0...
- Page 32 Timing is measured with a 50pf load and a 2.7K pull-up resistor on CON. Actual time will depend on system loading of CON. Delay from rising edge of CCLK to the release of dual-use pins to full user functionality. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 33 AT40K Series Configuration Mode 6: Slave Parallel Up Configuration Data Source: Parallel EEPROM, EPROM, PROM Dedicated Configuration Pins: RESET, CON, M , CCLK Dual-use I/O: , INIT, LDC, HDC, A Optional Dual-use I/O: CSOUT, CHECK, D Figure 18. Stand-alone 6 Parallel EEPROM System Application...
- Page 34 3. The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control register. Both are enabled by default after power-on-reset or manual reset. 4. Users must drive CON Low for 3 rising edges of CCLK, and then should release. 5. Data can also be loaded D<0:15> as a 16-bit word. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 35 AT40K Series Configuration Figure 20. Slave Parallel Up End of Configuration Download NO MORE CCLK CLOCKS NEEDED CONH 10K PULL-UP (INTERNAL) INIT USER I/O 20K PULL-UP (INTERNAL) USER I/O USER I/O (2)(3) D<0:7> USER I/O LAST BYTE, POSTAMBLE USER I/O...
- Page 36 The first is a stand-alone or cascade scheme whereby data comes from a microproces- sor, see Figure 21.The other is a cascade scheme where the data is driven by a parallel PROM, and the FPGA is usually downstream from a Mode 6 device, see Figure 22. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 37 AT40K Series Configuration Figure 22. Cascade 6 2 2 Parallel EEPROM AT40K AT40K AT40K Mode 6 Mode 2 Mode 2 Slave Parallel Low Slave Parallel Slave Parallel Optional IO Optional IO CHECK CHECK CHECK CLOCK CCLK CCLK CCLK CSOUT CSOUT CSOUT ADDR<0:19>...
- Page 38 3. The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control register. Both are enabled by default after power-on-reset or manual reset. 4. Users must drive CON Low for 3 rising edges of CCLK, and then should release. 5. Data can also be loaded D<0:15> as a 16-bit word. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 39 AT40K Series Configuration Figure 24. Slave Parallel End of Configuration Download NO MORE CCLK CLOCKS NEEDED CONH 10K PULL-UP (INTERNAL) USER I/O USER I/O INIT 20K PULL-UP (INTERNAL) USER I/O USER I/O USER I/O D<0:7> LAST BYTE OF POSTAMBLE DCSOUT...
- Page 40 Timing is measured with a 50pf load and a 2.7K pull-up resistor on CON. Actual time will depend on system loading of CON. Delay from rising edge of CCLK to the release of dual-use pins to full user functionality. AT40K Series Configuration 1009B–FPGA–03/02...
- Page 41 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.
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