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3.9 Timer/Counter Commands
3.9.1 Force Update
3.9.2 Force Restart
3.9.3 Force Hard Reset
4 Accessing 16-bit Registers
8045A-AVR-02/08
Equation 3-4. PWM Resolution, Dual Slope PWM Mode
The PWM base frequency depends on the period setting (PER[H:L]), system clock
frequency and clock prescaler and can be calculated using Equation 3-5.
Equation 3-5. Frequency calculation, Dual Slope PWM Mode
Where N represents the TC clock prescaler.
The Overflow Status Flag (OVFIF) or Compare Flag (CCxIF) can be used to generate
interrupts. If enabled, the interrupt service routine can be used for updating the period
and compare buffer values.
The CMD[1:0] bits in CTRLFSET are used to issue special commands to the TC.
These are described below.
The "Force update" command is used to force an UPDATE condition. Buffer registers
are copied to their destination when the UPDATE conditions are met. Issuing this
command forces an UPDATE condition regardless of the counter value. This can be
used to update both the period and compare registers at the exact same time. In input
capture mode, the "Force update" command only has effect on the PERBUF/PER
registers. See section 3.7 for more information about double buffered registers.
The "Force restart" command clears the CNT[H:L] registers and the direction bit to its
reset value.
The "Force hard reset" command puts all registers in that TC instance back to their
reset state. For safety reasons, the TC clock selection must be set to OFF for this
command to have any effect.
Since the XMEGA has a bus width of 8 bits, 16-bit registers are accessed as two 8-bit
registers. All accesses to 16-bit registers are performed using a hardware-controlled 8
bit temporary register to ensure concurrent update of the high and low byte registers.
Each Timer/Counter has one dedicated temporary register, TEMP, that is used for
this purpose. The TEMP register is shared for all 16-bit accesses in that TC module.
Usage of the TEMP register is automatically handled when the correct byte access
order is used, but it is important to understand the mechanism to avoid corruption of
registers.
Note that on the XMEGA, the byte order for multi-byte access is always from the least
significant byte to the most significant byte.
(
=
R
log
PER
PWM
_
DS
2
f
=
CLK
f
⋅
⋅
PWM
_
DS
2
N
PER
AVR1306
)
+
1
9
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