Page 1: Features
• Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port ATtiny13A – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit with Software Disable Function –...
Page 2: Pin Configurations
1. Pin Configurations Figure 1-1. Pinout of ATtiny13A 8-PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 PB2 (SCK/ADC1/T0/PCINT2) (PCINT4/ADC2) PB4 PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) 20-QFN/MLF (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) (PCINT4/ADC2) PB4 PB0 (MOSI/AIN0/OC0A/PCINT0) NOTE: Bottom pad should be soldered to ground.
Page 3: Pin Description
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13A as listed on page 1.1.4 RESET Reset input.
Page 4: Overview
2. Overview The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed.
Page 5 On-chip boot code running on the AVR core. The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
Page 6: About
3. About Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
Page 7: Cpu Core
ATtiny13A 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
Page 8: Alu - Arithmetic Logic Unit
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny13A 8126F–AVR–05/12...
Page 9 ATtiny13A 4.3.1 SREG – Status Register 0x3F SREG Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings.
Page 10: General Purpose Register File
The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 on page ATtiny13A 8126F–AVR–05/12...
Page 11: Stack Pointer
ATtiny13A Figure 4-3. The X-, Y-, and Z-registers X-register R27 (0x1B) R26 (0x1A) Y-register R29 (0x1D) R28 (0x1C) Z-register R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
Page 12: Instruction Execution Timing
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45. The list also determines the priority levels of the different interrupts. The lower the address the higher is the ATtiny13A 8126F–AVR–05/12...
Page 13 ATtiny13A priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
Page 14 A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny13A 8126F–AVR–05/12...
Page 15: Memories
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13A Pro- gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations.
Page 16: Eeprom Data Memory
Next Instruction EEPROM Data Memory The ATtiny13A contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
Page 17 ATtiny13A 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func- tion, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken.
Page 18 /* Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); Note: “Code Examples” on page ATtiny13A 8126F–AVR–05/12...
Page 19 ATtiny13A The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write...
Page 20: I/O Memory
“Register Summary” on page 158. All ATtiny13A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
Page 21 • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny13A. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
Page 22 The user should poll the EEPE bit before starting the read opera- tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEARL Register. ATtiny13A 8126F–AVR–05/12...
Page 23: System Clock And Clock Options
ATtiny13A 6. System Clock and Clock Options Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-...
Page 24: Clock Sources
To drive the device from an external clock source, CLKI should be driven as shown in Figure 6- 2. To run the device on an external clock, the CKSEL fuses must be programmed to “00”. Figure 6-2. External Clock Drive Configuration EXTERNAL CLKI CLOCK SIGNAL ATtiny13A 8126F–AVR–05/12...
Page 25 ATtiny13A When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-3. Table 6-3. Start-up Times for the External Clock Selection Start-up Time from Additional Delay Recommended SUT[1:0] Power-down and Power-save from Reset...
Page 26: System Clock Prescaler
8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. System Clock Prescaler The ATtiny13A system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 28.
Page 27: Register Description
Device Specific Calibration Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in ATtiny13A and it will always read zero. • Bits 6:0 – CAL[6:0]: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari- ations from the Oscillator frequency.
Page 28 CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock.
Page 29 ATtiny13A Table 6-8. Clock Prescaler Select (Continued) CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8126F–AVR–05/12...
Page 30: Power Management And Sleep Modes
Sleep Modes Figure 6-1 on page 23 presents the different clock systems in the ATtiny13A, and their distribu- tion. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources.
Page 31: Software Bod Disable
ATtiny13A Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled).
Page 32: Minimizing Power Consumption
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to “Interrupts” on page 45 for details on how to configure the Watchdog Timer. ATtiny13A 8126F–AVR–05/12...
Page 33: Register Description
ATtiny13A 7.4.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk...
Page 34 • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot be used when the ADC is shut down. ATtiny13A 8126F–AVR–05/12...
Page 35: System Control And Reset
ATtiny13A 8. System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump –...
Page 36: Reset Sources
Reset Sources The ATtiny13A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.
Page 37 External Reset During Operation 8.2.3 Brown-out Detection ATtiny13A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
Page 38: Internal Voltage Reference
Power-down mode. Watchdog Timer ATtiny13A has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
Page 39 ATtiny13A value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued. Figure 8-7. Watchdog Timer 128kHz OSCILLATOR WDP0 WDP1 WATCHDOG WDP2 RESET WDP3 MCU RESET WDTIF INTERRUPT WDTIE In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer.
Page 40 Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situa- ATtiny13A 8126F–AVR–05/12...
Page 41 ATtiny13A tion, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
Page 42: Register Description
See Bit Description • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Page 43 ATtiny13A This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Inter- rupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode.
Page 44 Table 8-2. Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator Typical Time-out at WDP3 WDP2 WDP1 WDP0 Cycles = 5.0V Reserved ATtiny13A 8126F–AVR–05/12...
Page 45: Interrupts
ATtiny13A 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13A. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page Interrupt Vectors The interrupt vectors of ATtiny13A are described in Table 9-1 below.
Page 46: External Interrupts
An example of timing of a pin change interrupt is shown in Figure 9-1 below. Figure 9-1. Timing of pin change interrupts pin_lat pcint_in_(0) PCINT(0) pcint_syn pcint_setflag pin_sync PCIF PCINT(0) in PCMSK(x) PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF ATtiny13A 8126F–AVR–05/12...
Page 47: Register Description
Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled.
Page 48 Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
Page 49: O Ports
ATtiny13A 10. I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Page 50: Ports As General Digital I/O
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. ATtiny13A 8126F–AVR–05/12...
Page 51 ATtiny13A If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
Page 52 In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK 0xFF INSTRUCTIONS out PORTx, r16 in r17, PINx SYNC LATCH PINxn 0x00 0xFF ATtiny13A 8126F–AVR–05/12...
Page 53 ATtiny13A The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Page 54: Alternate Port Functions
Pxn, PORT TOGGLE OVERRIDE ENABLE Note: WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk , SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATtiny13A 8126F–AVR–05/12...
Page 55 ATtiny13A The overriding signals may not be present in all port pins, but Figure 10-5 serves as a generic description applicable to all port pins in the AVR microcontroller family. Table 10-2 on page 55 summarizes the function of the overriding signals. The pin and port...
Page 56 PCINT4 • PCIE + ADC2D PCINT3 • PCIE + ADC3D PCIE + ADC0D) DIEOV ADC0D ADC2D ADC3D PCINT5 Input PCINT4 Input PCINT3 Input RESET Input, ADC0 Input ADC2 Input ADC3 Input Note: 1. 1 when the fuse is “0” (Programmed). ATtiny13A 8126F–AVR–05/12...
Page 57: Register Description
Initial Value • Bits 7, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Page 58 10.4.4 PINB – Port B Input Pins Address 0x16 – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write Initial Value ATtiny13A 8126F–AVR–05/12...
Page 59: 11 8-Bit Timer/Counter0 With Pwm
Figure 11-1 on page 59. For the actual placement of I/O pins, refer to “Pinout of ATtiny13A” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description”...
Page 60: Timer/Counter Clock Sources
Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler, see “Timer/Counter Prescaler” on page 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-2 shows a block diagram of the counter and its surroundings. ATtiny13A 8126F–AVR–05/12...
Page 61: Output Compare Unit
ATtiny13A Figure 11-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count Edge Detector clear TCNTn Control Logic direction ( From Prescaler ) bottom Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement.
Page 62 TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform ATtiny13A 8126F–AVR–05/12...
Page 63: Compare Match Output Unit
ATtiny13A generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in Normal mode.
Page 64: Modes Of Operation
(TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. ATtiny13A 8126F–AVR–05/12...
Page 65 ATtiny13A The timing diagram for the CTC mode is shown in Figure 11-5 on page 65. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. Figure 11-5. CTC Mode, Timing Diagram...
Page 66 The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result ATtiny13A 8126F–AVR–05/12...
Page 67 ATtiny13A in a constantly high or low output (depending on the polarity of the output set by the COM0A[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency of f /2 when OCR0A is set to zero.
Page 68: Timer/Counter Timing Diagrams
The figures include information on when Interrupt Flags are set. Figure 11-8 on page 69 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase cor- rect PWM mode. ATtiny13A 8126F–AVR–05/12...
Page 69 ATtiny13A Figure 11-8. Timer/Counter Timing Diagram, no Prescaling (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 11-9 shows the same timing data, but with the prescaler enabled. Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk...
Page 70: Register Description
COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM). Table 11-2. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description Normal port operation, OC0A disconnected. Toggle OC0A on Compare Match Clear OC0A on Compare Match Set OC0A on Compare Match ATtiny13A 8126F–AVR–05/12...
Page 71 ATtiny13A Table 11-3 shows the COM0A[1:0] bit functionality when the WGM0[1:0] bits are set to fast PWM mode. Table 11-3. Compare Output Mode, Fast PWM Mode COM0A1 COM0A0 Description Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected.
Page 72 Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 67 for more details. • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. ATtiny13A 8126F–AVR–05/12...
Page 73 ATtiny13A • Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-...
Page 74 The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “TCCR0A –...
Page 75 Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled.
Page 76 Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B –...
Page 77: Timer/Counter Prescaler
ATtiny13A 12. Timer/Counter Prescaler 12.1 Overview The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f ). Alternatively, one of four taps from the prescaler can be used CLK_I/O as a clock source.
Page 78: Register Description
Timer/Counter start counting. • Bit 0 – PSR10: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ATtiny13A 8126F–AVR–05/12...
Page 79: Analog Comparator
ATtiny13A 13. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate inter- rupt, exclusive to the Analog Comparator.
Page 80: Register Description
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13A and will always read as zero. ATtiny13A 8126F–AVR–05/12...
Page 81 ATtiny13A • Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 13-2 on page Table 13-2. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode Comparator Interrupt on Output Toggle.
Page 82: Analog To Digital Converter
Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler 14.2 Overview The ATtiny13A features a 10-bit successive approximation ADC. A block diagram of the ADC is shown in Figure 14-1. Figure 14-1. Analog to Digital Converter Block Schematic ADC CONVERSION...
Page 83: Operation
ATtiny13A The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion.
Page 84: Prescaling And Conversion Timing
7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. ATtiny13A 8126F–AVR–05/12...
Page 85 ATtiny13A The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
Page 86 ADSC remains high. Figure 14-7. ADC Timing Diagram, Free Running Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update ATtiny13A 8126F–AVR–05/12...
Page 87: Changing Channel Or Reference Selection
ATtiny13A For a summary of conversion times, see Table 14-1. Table 14-1. ADC Conversion Time Sample & Hold (Cycles Condition from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 Normal conversions Auto Triggered conversions 13.5 14.6 Changing Channel or Reference Selection The MUXn and REFS[1:0] bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
Page 88: Adc Noise Canceler
Figure 14-8. Analog Input Circuitry 1..100 kohm = 14 pF Note: The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. The value given is worst case. ATtiny13A 8126F–AVR–05/12...
Page 89: Analog Noise Canceling Techniques
ATtiny13A The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher imped- ance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely.
Page 90 • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 14-10. Gain Error Gain Output Code Error Ideal ADC Actual ADC Input Voltage ATtiny13A 8126F–AVR–05/12...
Page 91 ATtiny13A • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 14-11. Integral Non-linearity (INL) Output Code...
Page 92: Adc Conversion Result
Initial Value • Bits 7, 4:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – REFS0: Reference Selection Bit This bit selects the voltage reference for the ADC, as shown in Table 14-2.
Page 93 ATtiny13A • Bits 1:0 – MUX[1:0]: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. Table 14-3 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Page 94 When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. ATtiny13A 8126F–AVR–05/12...
Page 95 Initial Value • Bits 7, 5:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
Page 96: Debugwire On-Chip Debug System
MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL fuses. Figure 15-1. The debugWIRE Setup 1.8 - 5.5V dW(RESET) ATtiny13A 8126F–AVR–05/12...
Page 97: Software Break Points
ATtiny13A When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to V will not work.
Page 98: Self-Programming The Flash
Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. ATtiny13A 8126F–AVR–05/12...
Page 99: Performing A
ATtiny13A If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 16.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Page 100: Eeprom Write Prevents Writing To Spmcsr
2. Set RFLB and SELFPRGEN bits in SPMCSR. 3. Issuing an LPM instruction within three clock cycles will FLB in the destination register. If successful, the contents of the destination register are as follows. FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 ATtiny13A 8126F–AVR–05/12...
Page 101: Preventing Flash Corruption
ATtiny13A To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1...
Page 102: Register Description
Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.
Page 103: Memory Programming
This section describes how ATtiny13A memories can be programmed. 17.1 Program And Data Memory Lock Bits ATtiny13A provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 17-2 on page 103.
Page 104: Fuse Bytes
17.2 Fuse Bytes The ATtiny13A has two fuse bytes. Table 17-3 on page 104 Table 17-4 on page 104 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.
Page 105: Calibration Bytes
17.3 Calibration Bytes The signature area of the ATtiny13A contains two bytes of calibration data for the internal oscil- lator. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 9.6 MHz operation. During reset, this byte is automatically written into the OSCCAL register to ensure correct frequency of the oscillator.
Page 106: Serial Programming
Low: > 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f >= 12 MHz High: > 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f >= 12 MHz ATtiny13A 8126F–AVR–05/12...
Page 107 ATtiny13A 17.6.1 Serial Programming Algorithm When writing serial data to the ATtiny13A, data is clocked on the rising edge of SCK. When reading data from the ATtiny13A, data is clocked on the falling edge of SCK. See Figure 18-4 on page 122 Figure 18-3 on page 122 for timing details.
Page 108 103 for details. Write lock bits. Set bits = “0” to Write Lock Bits program lock bits. See Table 17-1 on 1010 1100 111x xxxx xxxx xxxx 11ii iiii page 103 for details. ATtiny13A 8126F–AVR–05/12...
Page 109: High-Voltage Serial Programming
= address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care 17.7 High-Voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, lock bits and fuse bits in the ATtiny13A. Figure 17-2. High-voltage Serial Programming +11.5 - 12.5V +1.8 - 5.5V (RESET) 8126F–AVR–05/12...
Page 110 Prog_enable[1] Prog_enable[2] 17.7.1 High-Voltage Serial Programming Algorithm To program and verify the ATtiny13A in the High-voltage Serial Programming mode, the follow- ing sequence is recommended (See instruction formats in Table 17-13 on page 111): The following algorithm puts the device in High-voltage Serial Programming mode: 1.
Page 111 4.5V 100 ns 5.5V 100 ns 17.7.2 High-Voltage Serial Programming Instruction set The instruction set is described in Table 17-13. Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr.3 until SDO goes...
Page 112 Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks Repeat Instr. 1 - 4 until the entire 0_00bb_bbbb_00 0_eeee_eeee_00 0_0000_0000_00 0_0000_0000_00 Load EEPROM page buffer is filled or until all data...
Page 113: Considerations For Efficient Programming
ATtiny13A Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks 0_0000_1000_00 0_0000_00bb_00 0_0000_0000_00 0_0000_0000_00 Read Signature Repeats Instr 2 4 for each 0_0100_1100_00 0_0000_1100_00 0_0110_1000_00 0_0110_1100_00 Bytes signature byte address.
Page 114 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny13A, data is clocked on the rising edge of the serial clock, see Figure 17-4 on page...
Page 115 ATtiny13A Figure 17-4. High-voltage Serial Programming Waveforms 17.8.3 Programming the EEPROM The EEPROM is organized in pages, see Table 18-9 on page 122. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be pro- grammed simultaneously.
Page 116 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 17-13 on page 111. 17.8.8 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V power off. ATtiny13A 8126F–AVR–05/12...
Page 117: Electrical Characteristics
ATtiny13A 18. Electrical Characteristics 18.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C...
Page 118: Speed
The maximum operating frequency of the device depends on supply voltage, V As shown in Figure 18-1, the relationship between maximum frequency and V is linear in the range of 1.8V to 4.5V. Figure 18-1. Maximum Frequency vs. V 20 MHz 4 MHz 1.8V 4.5V 5.5V ATtiny13A 8126F–AVR–05/12...
Page 119: Clock Characteristics
ATtiny13A 18.4 Clock Characteristics 18.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in...
Page 120: System And Reset Characteristics
V during the production test. This guar- antees that a Brown-out Reset will occur before V drops to a voltage where correct operation of the microcontroller is no longer guaranteed. ATtiny13A 8126F–AVR–05/12...
Page 121: Analog Comparator Characteristics
ATtiny13A 18.6 Analog Comparator Characteristics Table 18-7. Analog Comparator Characteristics, T = -40°C to +85°C Symbol Parameter Condition Units Input Offset Voltage = 5V, V < 10 Input Leakage Current = 5V, V = 2.7V Analog Propagation Delay (from saturation to slight overdrive) = 4.0V...
Page 122: Serial Programming Characteristics
SLSH CLCL = 1.8 – 5.5V MOSI Setup to SCK High OVSH CLCL MOSI Hold after SCK High SHOX CLCL Note: 1. 2 t for f < 12 MHz, 3 t for f >= 12 MHz CLCL CLCL ATtiny13A 8126F–AVR–05/12...
Page 123: High-Voltage Serial Programming Characteristics
ATtiny13A 18.9 High-voltage Serial Programming Characteristics Figure 18-5. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SLSH IVSH SHIX SCI (PB3) SHSL SDO (PB2) SHOV Table 18-10. High-voltage Serial Programming Characteristics = 25°C, V = 5.0V ± 10% (Unless otherwise noted)
Page 124: Typical Characteristics
ADC supply current I = 0.18 mA, and using Table 19-1 we find Timer/Counter0 supply current I = 0.004 mA. The total current consumption in idle mode is therefore I = 0.214 mA, approximately 0.21 mA. CCTOT ATtiny13A 8126F–AVR–05/12...
Page 125: Current Consumption In Active Mode
ATtiny13A 19.2 Current Consumption in Active Mode Figure 19-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 19-2.
Page 126 INTERNAL RC OSCILLATOR, 9.6 MHz 85 °C 25 °C -40 °C Figure 19-4. Active Supply Current vs. V (Internal RC Oscillator, 4.8 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4.8 MHz 85 °C 25 °C -40 °C ATtiny13A 8126F–AVR–05/12...
Page 127 ATtiny13A Figure 19-5. Active Supply Current vs. V (Internal WDT Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL WD OSCILLATOR, 128 KHz 0.12 25 °C -40 °C 85 °C 0.08 0.06 0.04 0.02 Figure 19-6. Active Supply Current vs. V (32 kHz External Clock) ACTIVE SUPPLY CURRENT vs.
Page 128: Current Consumption In Idle Mode
1.8 V 0.02 Frequency (MHz) Figure 19-8. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) ATtiny13A 8126F–AVR–05/12...
Page 129 ATtiny13A Figure 19-9. Idle Supply Current vs. V (Internal RC Oscillator, 9.6 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 9.6 MHz 85 °C 25 °C -40 °C Figure 19-10. Idle Supply Current vs. V (Internal RC Oscillator, 4.8 MHz) IDLE SUPPLY CURRENT vs.
Page 130 85 °C 0.015 0.01 0.005 Figure 19-12. Idle Supply Current vs. V (32 kHz External Clock) IDLE SUPPLY CURRENT vs. V 32 KHz EXTERNAL OSCILLATOR, PRR=0xFF 0.006 0.005 85 °C 25 °C -40 °C 0.004 0.003 0.002 0.001 ATtiny13A 8126F–AVR–05/12...
Page 131: Current Consumption In Power-Down Mode
ATtiny13A 19.4 Current Consumption in Power-down Mode Figure 19-13. Power-down Supply Current vs. V (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 85 °C -40 °C 25 °C Figure 19-14. Power-down Supply Current vs. V (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
Page 132: Current Consumption In Reset
Figure 19-16. Reset Supply Current vs. V (1 - 20 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. V EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) ATtiny13A 8126F–AVR–05/12...
Page 133: Current Consumption Of Peripheral Units
ATtiny13A 19.6 Current Consumption of Peripheral Units Figure 19-17. Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V 85 °C 25 °C -40 °C Figure 19-18. ADC Current vs. V ADC CURRENT vs. V f = 1.0 MHz 85 °C 25 °C...
Page 134 ANALOG COMPARATOR CURRENT vs. V f = 1.0 MHz 85 °C 25 °C -40 °C Figure 19-20. Programming Current vs. V PROGRAMMING CURRENT vs. V 9000 8000 -40 °C 7000 25 °C 6000 85 °C 5000 4000 3000 2000 1000 ATtiny13A 8126F–AVR–05/12...
Page 135: Pull-Up Resistors
ATtiny13A 19.7 Pull-up Resistors Figure 19-21. Pull-up Resistor Current vs. Input Voltage (I/O Pin, V = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 1.8V 25 °C 85 °C -40 °C Figure 19-22. Pull-up Resistor Current vs. Input Voltage (I/O Pin, V = 3V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Page 136 = 5V 85 °C 25 °C -40 °C Figure 19-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE = 1.8V 25 °C -40 °C 85 °C RESET ATtiny13A 8126F–AVR–05/12...
Page 137 ATtiny13A Figure 19-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 3V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE = 3V 25 °C -40 °C 85 °C RESET Figure 19-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5V) RESET PULL-UP RESISTOR CURRENT vs.
Page 138: Output Driver Strength (Low Power Pins)
(mA) Figure 19-28. V : I/O Pin Output Voltage vs. Source Current (Low Power Pins, V = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS, V = 3V -40 °C 25 °C 85 °C (mA) ATtiny13A 8126F–AVR–05/12...
Page 139 ATtiny13A Figure 19-29. V : I/O Pin Output Voltage vs. Source Current (Low Power Pins, V = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS, V = 5V -40 °C 25 °C 85 °C (mA) Figure 19-30. V : I/O Pin Output Voltage vs.
Page 140 (mA) Figure 19-32. V : I/O Pin Output Voltage vs. Sink Current (Low Power Pins, V = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT LOW POWER PINS, V = 5V 85 °C 25 °C -40 °C (mA) ATtiny13A 8126F–AVR–05/12...
Page 141: Output Driver Strength (Regular Pins)
ATtiny13A 19.9 Output Driver Strength (Regular Pins) Figure 19-33. V : I/O Pin Output Voltage vs. Source Current (V = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 1.8V -40 °C 25 °C 85 °C (mA) Figure 19-34. V : I/O Pin Output Voltage vs.
Page 142 85 °C (mA) Figure 19-36. V : I/O Pin Output Voltage vs. Sink Current (V = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 1.8V 85 °C 0.45 25 °C 0.35 -40 °C 0.25 0.15 0.05 (mA) ATtiny13A 8126F–AVR–05/12...
Page 143 ATtiny13A Figure 19-37. V : I/O Pin Output Voltage vs. Sink Current (V = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 3V 0.45 85 °C 0.35 25 °C -40 °C 0.25 0.15 0.05 (mA) Figure 19-38. V : I/O Pin Output Voltage vs. Sink Current (V = 5V) I/O PIN OUTPUT VOLTAGE vs.
Page 144 25 °C 85 °C (mA) Figure 19-40. V : Reset Pin as I/O, Output Voltage vs. Source Current (V = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 3V -40 °C 25 °C 85 °C (mA) ATtiny13A 8126F–AVR–05/12...
Page 145 ATtiny13A Figure 19-41. V : Reset Pin as I/O, Output Voltage vs. Source Current (V = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 5V -40 °C 25 °C 85 °C (mA) Figure 19-42. V : Reset Pin as I/O, Output Voltage vs. Sink Current (V = 1.8V)
Page 146 25 °C -40 °C (mA) Figure 19-44. V : Reset Pin as I/O, Output Voltage vs. Sink Current (V = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 5V 85 °C 25 °C -40 °C (mA) ATtiny13A 8126F–AVR–05/12...
Page 147: Input Thresholds And Hysteresis (For I/O Ports)
ATtiny13A 19.10 Input Thresholds and Hysteresis (for I/O Ports) Figure 19-45. V : Input Threshold Voltage vs. V (I/O Pin, Read as '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC , I/O PIN READ AS '1' 85 °C 25 °C -40 °C...
Page 148 25 °C 85 °C Figure 19-48. V : Input Threshold Voltage vs. V (Reset Pin as I/O, Read as '1') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC , RESET READ AS '1' -40 °C 25 °C 85 °C ATtiny13A 8126F–AVR–05/12...
Page 149 ATtiny13A Figure 19-49. V : Input Threshold Voltage vs. V (Reset Pin as I/O, Read as '0') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC , RESET READ AS '0' 85 °C 25 °C -40 °C Figure 19-50. V : Input Hysteresis vs. V (Reset Pin as I/O) RESET PIN AS IO, INPUT HYSTERESIS vs.
Page 150: Bod, Bandgap And Reset
Figure 19-51. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 4.3V RISING 4.35 FALLING 4.25 Temperature (C) Figure 19-52. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 2.7V RISING 2.75 FALLING 2.65 Temperature (C) ATtiny13A 8126F–AVR–05/12...
Page 151 ATtiny13A Figure 19-53. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL = 1.8V 1.85 RISING FALLING 1.75 Temperature (C) Figure 19-54. Bandgap Voltage vs. V BANDGAP VOLTAGE vs. V 1.14 1.12 85 °C 25 °C -40 °C 1.08...
Page 152 -40 °C 25 °C 85 °C Figure 19-56. V : Reset Input Threshold Voltage vs. V (Reset Pin Read as '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC , I/O PIN READ AS '0' 85 °C 25 °C -40 °C ATtiny13A 8126F–AVR–05/12...
Page 153 ATtiny13A Figure 19-57. V : Reset Input Pin Hysteresis vs. V RESET PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C Figure 19-58. Minimum Reset Pulse Width vs. V MINIMUM RESET PULSE WIDTH vs. V 2000 1500 1000 85 °C...
Page 154: Internal Oscillator Speed
CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 4.5 V 2.7 V 1.8 V Temperature (C) Figure 19-60. Calibrated 9.6 MHz RC Oscillator Frequency vs. V CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 85 °C 25 °C -40 °C ATtiny13A 8126F–AVR–05/12...
Page 155 ATtiny13A Figure 19-61. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE = 3V 25 °C OSCCAL Figure 19-62. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.8 V...
Page 156 CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 85 °C 25 °C -40 °C Figure 19-64. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE = 3V 25 °C OSCCAL ATtiny13A 8126F–AVR–05/12...
Page 157 ATtiny13A Figure 19-65. 128 kHz Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 116000 114000 112000 -40 °C 25 °C 110000 108000 106000 85 °C 104000 102000 100000 Figure 19-66. 128 kHz Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs.
Page 158: Register Summary
ADCH ADC Data Register High Byte page 94 0x04 ADCL ADC Data Register Low Byte page 94 0x03 ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 pages 80, 0x02 Reserved – 0x01 Reserved – 0x00 Reserved – ATtiny13A 8126F–AVR–05/12...
Page 159 ATtiny13A Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are...
Page 160: Instruction Set Summary
Set Bit in I/O Register None I/O(P,b) ← 0 Clear Bit in I/O Register None Rd(n+1) ← Rd(n), Rd(0) ← 0 Logical Shift Left Z,C,N,V Rd(n) ← Rd(n+1), Rd(7) ← 0 Logical Shift Right Z,C,N,V Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V ATtiny13A 8126F–AVR–05/12...
Page 161 ATtiny13A Mnemonics Operands Description Operation Flags #Clocks Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V Rd(n) ← Rd(n+1), n=0..6 Arithmetic Shift Right Z,C,N,V SWAP Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None SREG(s) ← 1 BSET Flag Set SREG(s) SREG(s) ← 0 BCLR Flag Clear SREG(s) T ←...
Page 162: Ordering Information
– 2nd Line: Axx – 3rd Line: xxx 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities. 5. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny13A Specification at 105°C.
Page 163: Packaging Information
ATtiny13A 23. Packaging Information 23.1 Top View End View COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL NOTE A2 A 0.210 0.115 0.130 0.195 0.014 0.018 0.022 0.045 0.060 0.070 0.030 0.039 0.045 0.008 0.010 0.014 0.355 0.365 0.400 0.005 0.300...
Page 164 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 4/15/08 TITLE DRAWING NO. REV. 8S2, 8-lead, 0.208” Body, Plastic Small Package Drawing Contact: Outline Package (EIAJ) packagedrawings@atmel.com ATtiny13A 8126F–AVR–05/12...
Page 165 ATtiny13A 23.3 Top View COMMON DIMENSIONS (Unit of Measure = mm) Side View NOTE SYMBOL – – 1.75 – – 0.51 – – 0.25 – – 5.00 – – 4.00 1.27 BSC – – 6.20 – – 1.27 End View Note: This drawing is for general information only.
Page 166 0.35 0.40 0.55 10/27/04 TITLE DRAWING NO. REV. 2325 Orchard Parkway 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) San Jose, CA 95131 ATtiny13A 8126F–AVR–05/12...
Page 167 ATtiny13A 23.5 10M1 Pin 1 ID SIDE VIEW TOP VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL NOTE 0.80 0.90 1.00 0.00 0.02 0.05 0.18 0.25 0.30 2.90 3.00 3.10 1.40 – 1.75 2.90 3.00 3.10 2.20 – 2.70 0.50...
Page 168 24. Errata The revision letters in this section refer to the revision of the ATtiny13A device. 24.1 ATtiny13A Rev. G – H • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the EEPROM at V below 1.9 volts might fail.
Page 169 ATtiny13A 25. Datasheet Revision History Please note that page numbers in this section refer to the current version of this document and may not apply to previous versions. 25.1 Rev. 8126F – 05/12 1. Updated Table 10-5 on page 2. Updated order codes on page 162.
Page 170 32 – Added register description on page 33 – Updated Register Summary on page 158 8. Added description of enhanced function, “Enhanced Power-On Reset”: – Updated Table 18-4 on page 120, and Table 18-5 on page 120 ATtiny13A 8126F–AVR–05/12...
Page 171: Table Of Contents
ATtiny13A Table of Contents Features ..................... 1 Pin Configurations ................... 2 Pin Description ....................3 Overview ....................4 Block Diagram ....................4 About ......................6 Resources ......................6 Code Examples ....................6 Data Retention ....................6 CPU Core ....................7 Architectural Overview ..................7 ALU – Arithmetic Logic Unit ................8 Status Register ....................8...
Page 172 Timer/Counter Timing Diagrams ..............68 11.9 Register Description ..................70 12 Timer/Counter Prescaler ............... 77 12.1 Overview ......................77 12.2 Prescaler Reset ....................77 12.3 External Clock Source ..................77 12.4 Register Description..................78 13 Analog Comparator ................79 13.1 Analog Comparator Multiplexed Input .............79 ATtiny13A 8126F–AVR–05/12...
Page 173 ATtiny13A 13.2 Register Description ..................80 14 Analog to Digital Converter ..............82 14.1 Features ......................82 14.2 Overview ......................82 14.3 Operation ......................83 14.4 Starting a Conversion ..................83 14.5 Prescaling and Conversion Timing ..............84 14.6 Changing Channel or Reference Selection .............87 14.7 ADC Noise Canceler ..................88...
Page 174 19.11 BOD, Bandgap and Reset ................150 19.12 Internal Oscillator Speed ................154 20 Register Summary ................158 21 Instruction Set Summary ..............160 22 Ordering Information ................162 23 Packaging Information ................ 163 23.1 8P3 ........................163 23.2 8S2 ........................164 ATtiny13A 8126F–AVR–05/12...
Page 175 8S1 ........................165 23.4 20M1 ......................166 23.5 10M1 ......................167 24 Errata ..................... 168 24.1 ATtiny13A Rev. G – H ...................168 24.2 ATtiny13A Rev. E – F ..................168 24.3 ATtiny13 Rev. A – D ..................168 25 Datasheet Revision History ..............169 25.1 Rev.
Page 176 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

Atmel ATtiny13A Manual

Features

1 Pin Configurations

2 Overview

3 About

4 CPU Core

5 Memories

6 System Clock and Clock Options

7 Power Management and Sleep Modes

8 System Control and Reset

9 Interrupts

10 O Ports

11 8-Bit Timer/Counter0 with PWM

12 Timer/Counter Prescaler

13 Analog Comparator

14 Analog to Digital Converter

15 Debugwire On-Chip Debug System

16 Self-Programming the Flash

17 Memory Programming

18 Electrical Characteristics

19 Typical Characteristics

20 Register Summary

21 Instruction Set Summary

22 Ordering Information

23 Packaging Information

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Table of Contents