Block Diagram - Atmel ATtiny25 Manual

2.1

Block Diagram

7598H–AVR–07/09
Figure 2-1. Block Diagram
PROGRAM
COUNTER
VCC
PROGRAM
FLASH
GND
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
8-BIT DATABUS
STACK WATCHDOG
POINTER
MCU CONTROL
SRAM
MCU STATUS
GENERAL
PURPOSE
REGISTERS
X
Y
Z
UNIVERSAL
ALU
INTERFACE
INTERRUPT
STATUS
REGISTER
DATA REGISTER DATA DIR.
PORT B REG.PORT B
PORT B DRIVERS
PB0-PB5
ATtiny25/45/85
CALIBRATED
INTERNAL
OSCILLATOR
TIMING AND
TIMER CONTROL
REGISTER
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
SERIAL
UNIT
DATA
OSCILLATORS
EEPROM
ADC /
ANALOG COMPARATOR
RESET
3