Universal Serial Interface - Usi; Overview - Atmel ATtiny25 Manual

16. Universal Serial Interface – USI
16.1

Overview

ATtiny25/45/85
96
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load. The main features of the USI are:
•
Two-wire Synchronous Data Transfer (Master or Slave, f
•
Three-wire Synchronous Data Transfer (Master or Slave f
•
Data Received Interrupt
•
Wakeup from Idle Mode
•
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
•
Two-wire Start Condition Detector with Interrupt Capability
A simplified block diagram of the USI is shown on Figure 16-1. For the actual placement of I/O
pins, refer to "Pinout ATtiny25/45/85" on page
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the "USI Register Descriptions" on page
Figure 16-1. Universal Serial Interface, Block Diagram
USIDR
USIDB
USISR
2
USICR
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock
source.
2. CPU accessible I/O Registers, including I/O
103.
D Q
LE
3
2
1
0
3
2
4-bit Counter
1
0
[1]
= f /16)
SCLmax CK
= f /4)
SCKmax CK
DO
DI/SDA
TIM0 COMP
0
USCK/SCL
1
CLOCK
HOLD
Two-wire Clock
Control Unit
(Output only)
(Input/Open Drain)
(Input/Open Drain)
7598H–AVR–07/09