Mcu Control Register - Mcucr; General Interrupt Mask Register - Gimsk - Atmel ATtiny25 Manual

11.1 MCU Control Register – MCUCR
11.2 General Interrupt Mask Register – GIMSK
7598H–AVR–07/09
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 7
BODS
Read/Write R/W
Initial Value 0
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 11-1. Interrupt 0 Sense Control
ISC01 ISC00
0 0
0 1
1 0
1 1
Bit 7
–
Read/Write R
Initial Value 0
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from
the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0 Register.
6 5 4
PUD SE SM1
R/W R/W R/W
0 0 0
Table 11-1. The value on the INT0 pin is sampled before detecting
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
6 5 4
INT0 PCIE –
R/W R/W R
0 0 0
ATtiny25/45/85
3 2 1
SM0 BODSE ISC01
R/W R/W R/W
0 0 0
3 2 1
– – –
R R R
0 0 0
0
ISC00 MCUCR
R/W
0
0
– GIMSK
R
0
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