Interrupts; Interrupt Vectors In Attiny25/45/85 - Atmel ATtiny25 Manual

8.10.2 Safety Level 2

9. Interrupts

9.1

Interrupt Vectors in ATtiny25/45/85

7598H–AVR–07/09
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
always is set, the WDE must be written to one to start the timed sequence.
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85.
For a general explanation of the AVR interrupt handling, refer to
on page 11.
Table 9-1. Reset and Interrupt Vectors
Vector Program
No. Address
1 0x0000
2 0x0001
3 0x0002
4 0x0003
5 0x0004
6 0x0005
7 0x0006
8 0x0007
9 0x0008
10 0x0009
11 0x000A
12 0x000B
13 0x000C
14 0x000D
15 0x000E
Source Interrupt Definition
External Pin, Power-on Reset, Brown-out Reset,
RESET
Watchdog Reset
INT0 External Interrupt Request 0
PCINT0 Pin Change Interrupt Request 0
TIM1_COMPA Timer/Counter1 Compare Match A
TIM1_OVF Timer/Counter1 Overflow
TIM0_OVF Timer/Counter0 Overflow
EE_RDY EEPROM Ready
ANA_COMP Analog Comparator
ADC ADC Conversion Complete
TIM1_COMPB Timer/Counter1 Compare Match B
TIM0_COMPA Timer/Counter0 Compare Match A
TIM0_COMPB Timer/Counter0 Compare Match B
WDT Watchdog Time-out
USI_START USI START
USI_OVF USI Overflow
ATtiny25/45/85
"Reset and Interrupt Handling"
45