Atmel ATtiny26 Manual
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Atmel ATtiny26 Manual

8-bit avr microcontroller with 2k bytes flash
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Features
•
High-performance, Low-power AVR
•
RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
•
Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– 8-bit Timer/Counter with Separate Prescaler
– 8-bit High-speed Timer with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Non-overlapping Inverted PWM Output Pins
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
8 Differential ADC Channels
7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– On-chip Analog Comparator
– External Interrupt
– Pin Change Interrupt on 11 Pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
•
Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator
•
I/O and Packages
– 20-lead PDIP/SOIC: 16 Programmable I/O Lines
– 32-lead QFN/MLF: 16 programmable I/O Lines
•
Operating Voltages
– 2.7V - 5.5V for ATtiny26L
– 4.5V - 5.5V for ATtiny26
•
Speed Grades
– 0 - 8 MHz for ATtiny26L
– 0 - 16 MHz for ATtiny26
•
Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L
– Active 16 MHz, 5V and 25°C: Typ 15 mA
– Active 1 MHz, 3V and 25°C: 0.70 mA
– Idle Mode 1 MHz, 3V and 25°C: 0.18 mA
– Power-down Mode: < 1 µA
®
8-bit Microcontroller
8-bit
Microcontroller
with 2K Bytes
Flash
ATtiny26
ATtiny26L
Rev. 1477G–AVR–03/05
1477G–AVR–03/05

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Summary of Contents for Atmel ATtiny26

  • Page 1: Table Of Contents Features

    – 4.5V - 5.5V for ATtiny26 • Speed Grades – 0 - 8 MHz for ATtiny26L – 0 - 16 MHz for ATtiny26 • Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L – Active 16 MHz, 5V and 25°C: Typ 15 mA –...

  • Page 2: Pin Configuration

    (ADC9/INT0/T0) PB6 PA6 (ADC5/AIN0) (ADC10/RESET) PB7 PA7 (ADC6/AIN1) MLF Top View PA2 (ADC2) (OC1B) PB3 PA3 (AREF) AVCC (ADC7/XTAL1) PB4 PA4 (ADC3) (ADC8/XTAL2) PB5 Note: Note: The bottom pad under the QFN/MLF package should be soldered to ground. ATtiny26(L) 1477G–AVR–03/05...

  • Page 3: Description

    20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the PWM outputs have inverted non-overlapping output pins ideal for synchronous rectifica- tion.

  • Page 4: Block Diagram

    Block Diagram Figure 1. The ATtiny26(L) Block Diagram 8-BIT DATA BUS INTERNAL INTERNAL CALIBRATED OSCILLATOR OSCILLATOR PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL PROGRAM REGISTER SRAM FLASH AVCC MCU STATUS REGISTER INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS...

  • Page 5: Pin Descriptions

    ATtiny26(L) Pin Descriptions Digital supply voltage pin. Digital ground pin. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to V , even if the ADC is not used. If the ADC is used, it should be connected to V through a low-pass filter.

  • Page 6: Avr Cpu Core

    The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 2 shows the ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the Register File as well.

  • Page 7: General Purpose Register File

    ATtiny26(L) The AVR uses a Harvard architecture concept with separate memories and buses for program and data memories. The program memory is accessed with a two stage pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle.

  • Page 8: Alu - Arithmetic Logic Unit

    The high-performance AVR ALU operates in direct connection with all 32 general pur- Unit pose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed. The ALU operations are divided into three main catego- ries – Arithmetic, Logical, and Bit-functions. ATtiny26(L) 1477G–AVR–03/05...

  • Page 9: Status Register - Sreg

    ATtiny26(L) Status Register – SREG The AVR Status Register – SREG – at I/O space location $3F is defined as: $3F ($5F) SREG Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the Interrupt Mask Registers –...

  • Page 10: Stack Pointer - Sp

    Stack Pointer – SP The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space loca- tion $3D ($5D). As the ATtiny26(L) data memory has 224 ($E0) locations, eight bits are used. $3D ($5D) Read/Write Initial Value The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter- rupt Stacks are located.
  • Page 11 ATtiny26(L) Register Direct, Two Registers Figure 6. Direct Register Addressing, Two Registers Rd and Rr Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 7. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word.
  • Page 12 $0000 X-, Y-, OR Z-REGISTER $00DF Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Pre- Figure 11. Data Indirect Addressing with Pre-decrement decrement Data Space $0000 X-, Y-, OR Z-REGISTER $00DF ATtiny26(L) 1477G–AVR–03/05...
  • Page 13 ATtiny26(L) The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register. Data Indirect with Post- Figure 12. Data Indirect Addressing with Post-increment increment Data Space $0000 X-, Y-, OR Z-REGISTER $00DF The X-, Y-, or Z-register is incremented after the operation.
  • Page 14 Z-register). Relative Program Addressing, Figure 15. Relative Program Memory Addressing RJMP and RCALL PROGRAM MEMORY $000 $3FF Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047. ATtiny26(L) 1477G–AVR–03/05...

  • Page 15: Memories

    ATtiny26(L) Memories The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 16 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.

  • Page 16: In-System Programmable Flash Program Memory

    1K x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny26(L) Program Counter – PC – is 10 bits wide, thus addressing the 1024 program memory addresses, see “Memory Programming” on page 107 for a detailed description on Flash data downloading.

  • Page 17: Eeprom Data Memory

    EEPROM Data Memory The ATtiny26(L) contains 128 bytes of data EEPROM memory. It is organized as a sep- arate data space, in which single bytes can be read and written (see “Memory Programming” on page 107). The EEPROM has an endurance of at least 100,000 write/erase cycles per location.
  • Page 18 Initial Value • Bit 7..4 – RES: Reserved Bits These bits are reserved bits in the ATtiny26(L) and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled.
  • Page 19 ATtiny26(L) • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register.

  • Page 20: I/O Memory

    I/O Memory The I/O space definition of the ATtiny26(L) is shown in Table 2 Table 2. ATtiny26(L) I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3D ($5D) Stack Pointer $3B ($5B) GIMSK General Interrupt Mask Register $3A ($5A)
  • Page 21 1. Reserved and unused locations are not shown in the table. All ATtiny26(L) I/O and peripheral registers are placed in the I/O space. The I/O loca- tions are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space.

  • Page 22: System Clock And Clock Options

    ADC Clock – clk The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu- rate ADC conversion results. ATtiny26(L) 1477G–AVR–03/05...
  • Page 23 ATtiny26(L) Internal PLL for Fast The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from Peripheral Clock Generation – nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is automatically divided down to 1 MHz, if needed.

  • Page 24: Clock Sources

    Reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for ATtiny26(L) 1477G–AVR–03/05...

  • Page 25: Default Clock Source

    ATtiny26(L) each time-out is shown in Table 5. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. Table 5. Number of Watchdog Oscillator Cycles Typ Time-out (V = 5.0V) Typ Time-out (V = 3.0V) Number of Cycles 4.1 ms...

  • Page 26: Low-Frequency Crystal Oscillator

    Fast rising power or BOD enabled 1K CK 65 ms Slowly rising power 32K CK 65 ms Stable frequency at start-up Reserved Note: 1. These options should only be used if frequency stability at start-up is not important for the application. ATtiny26(L) 1477G–AVR–03/05...

  • Page 27: External Rc Oscillator

    ATtiny26(L) External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 23 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor.

  • Page 28: Calibrated Internal Rc Oscillator

    At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre- quency within ± 3% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V and Temperature.

  • Page 29: External Clock

    ATtiny26(L) will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency.

  • Page 30: High Frequency Pll Clock - Pllclk

    Start-up Time from Additional Delay from SUT1..0 Power-down Reset (V = 5.0V) Recommended Usage 1K CK – BOD enabled 1K CK 4.1 ms Fast rising power 1K CK 65 ms Slowly rising power 16K CK – Slowly rising power ATtiny26(L) 1477G–AVR–03/05...

  • Page 31: System Control And Reset

    Figure 25 shows the reset logic for the ATtiny26(L). Table 16 shows the timing and electrical parameters of the reset circuitry for ATtiny26(L).

  • Page 32: Power-On Reset

    The test is performed using BODLEVEL=1 for ATtiny26L and BODLEVEL=0 for ATtiny26. BODLEVEL=1 is not applicable for ATtiny26. See start-up times from reset from “System Clock and Clock Options” on page 22.

  • Page 33: External Reset

    ATtiny26(L) Figure 26. MCU Start-up, RESET Tied to VCC RESET TOUT TIME-OUT INTERNAL RESET Figure 27. MCU Start-up, RESET Controlled Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running.

  • Page 34: Brown-Out Detection

    Brown-out Detection ATtiny26(L) has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and V decreases below the trigger level, the Brown-out Reset is immediately activated. When V increases above the trigger level, the Brown-out Reset is deactivated after a delay.

  • Page 35: Mcu Status Register - Mcusr

    See Bit Description • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set (one) if a Watchdog Reset occurs. The bit is reset (zero) by a Power-on Reset, or by writing a logic zero to the flag.

  • Page 36: Power Management And Sleep Modes

    Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Table 19 on page 38 presents the different clock systems in the ATtiny26, and their dis- tribution. The figure is helpful in selecting an appropriate sleep mode.

  • Page 37: Idle Mode

    ATtiny26(L) • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set (one). The activity on the external INT0 pin that acti- vates the interrupt is defined in the following table.

  • Page 38: Standby Mode

    INT0, and Pin USI Start EEPROM Other I/O Sleep Mode FLASH Source Enabled Change Condition Ready Idle ADC Noise Reduction Power-down Standby Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2. Only level interrupt INT0. ATtiny26(L) 1477G–AVR–03/05...

  • Page 39: Minimizing Power Consumption

    ATtiny26(L) Minimizing Power There are several issues to consider when trying to minimize the power consumption in Consumption an AVR controlled system. In general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device’s functions are operating.
  • Page 40 V /2, the input buffer will use excessive power. ATtiny26(L) 1477G–AVR–03/05...

  • Page 41: I/O Ports

    ATtiny26(L) I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).

  • Page 42: Ports As General Digital I/O

    PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the ATtiny26(L) 1477G–AVR–03/05...
  • Page 43 ATtiny26(L) difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
  • Page 44 In this case, the delay t through the synchronizer is one system clock period. Figure 34. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK 0xFF INSTRUCTIONS out PORTx, r16 in r17, PINx SYNC LATCH PINxn 0x00 0xFF ATtiny26(L) 1477G–AVR–03/05...
  • Page 45 ATtiny26(L) The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

  • Page 46: Alternate Port Functions

    ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATtiny26(L) 1477G–AVR–03/05...
  • Page 47 ATtiny26(L) Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 35 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 22. Generic Description of Overriding Signals for Alternate Functions...
  • Page 48 The masking alternate function is the Analog Comparator. Digital input is enabled on pin PA7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. • ADC5/AIN0 Port – A, Bit 6 ATtiny26(L) 1477G–AVR–03/05...
  • Page 49 ATtiny26(L) AIN0: Analog Comparator Positive input and ADC5: ADC input channel 5 Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator or analog to digital converter.
  • Page 50 1. Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE1 flag in GIMSK is set and the alternate function of the pin is dis- abled as described in “Pin Change Interrupt” on page 62 2. Not operator is marked with “~”. ATtiny26(L) 1477G–AVR–03/05...
  • Page 51 ATtiny26(L) Alternate Functions Of Port B Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI pro- gramming and pin change interrupt. The ADC is described in “Analog to Digital Converter” on page 94, Clocking in “AVR CPU Core” on page 6, timers in “Timer/Counters”...
  • Page 52 The masking alternate functions are the XTAL1 inputs. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions. • OC1B/PCINT0 – Port B, Bit 3 ATtiny26(L) 1477G–AVR–03/05...
  • Page 53 ATtiny26(L) OC1B: Output Compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode.
  • Page 54 5. Not operator is marked with “~”. 6. The operation of the Timer/Counter0 with external clock disabled is described in “8-bit Timer/Counter0” on page 65. 7. External clock is selected by the PLLCK and CKSEL Fuses as described in “Clock Sources” on page 24. ATtiny26(L) 1477G–AVR–03/05...
  • Page 55 ATtiny26(L) Table 28. Overriding Signals for Alternate Functions in PB3..PB0 PB2/SCK/SCL/OC1B/PCI Signal Name PB3/OC1B/PCINT0 PB1/DO/OC1A/PCINT0 PB0/DI/SDA/OC1A PUOE USI_TWO-WIRE USI_TWO-WIRE PUOV DDOE USI_TWO-WIRE USI_TWO-WIRE DDOV (USI_SCL_HOLD (~SDA | ~PORTB0) • PORTB2) • DDB2 DDB0 PVOE OC1B_ENABLE USI_TWO-WIRE • USI_THREE-WIRE USI_TWO-WIRE • DDB0...

  • Page 56: Register Description For I/O Ports

    Port B Data Direction Register – DDRB $17 ($37) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write Initial Value Port B Input Pins Address – PINB $16 ($36) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write Initial Value ATtiny26(L) 1477G–AVR–03/05...

  • Page 57: Interrupts

    Interrupts Interrupt Vectors The ATtiny26(L) provides eleven interrupt sources. These interrupts and the separate Reset Vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.

  • Page 58: Interrupt Handling

    Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
  • Page 59 Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. • Bit 6 – INTF0: External Interrupt Flag0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
  • Page 60 Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. • Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 compare match A, interrupt is enabled.
  • Page 61 TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. 1477G–AVR–03/05...

  • Page 62: External Interrupt

    This implies that one external event might cause several interrupts. The value of the programmed fuse is “0” and unprogrammed is “1”. Each of the lines enables the alternate function so “or” function of the lines enables the function. ATtiny26(L) 1477G–AVR–03/05...
  • Page 63 ATtiny26(L) Table 30. Alternative Functions Control Register[Bit Name] which Bit or Fuse Alternate Function set the Alternate Function Value AREF ADMUX[REFS0] Analog Comparator ACSR[ACD] Analog Comparator ACSR[ACD] USI Two-wire mode USICR[USIWM1] USI Three-wire mode USICR[USIWM1,USIWM0] TC1 compare/PWM TCCR1A[COM1A1,COM1A0,PWM1A] USI Three-wire mode...

  • Page 64: Timer/Counters

    Timer/Counters The ATtiny26(L) provides two general purpose 8-bit Timer/Counters. The Timer/Counters have separate prescaling selection from the separate prescaler. The Timer/Counter0 clock (CK) as the clock timebase. The Timer/Counter1 has two clocking modes, a synchronous mode and an asynchronous mode. The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.

  • Page 65: Timer/Counter1 Prescaler

    ATtiny26(L) Timer/Counter1 Figure 37 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections Prescaler are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384 and stop in synchronous. The clock options are described in Table 34 on page 72 and the Timer/Counter1 Control Register, TCCR1B.
  • Page 66 Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 3 – PSR0: Prescaler Reset Timer/Counter0 When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed.

  • Page 67: 8-Bit Timer/Counter1

    ATtiny26(L) The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual Data Direction Control Register (cleared to zero gives an input pin).
  • Page 68 Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control val- ues are lost. The following Figure 40 shows the block diagram for Timer/Counter1. ATtiny26(L) 1477G–AVR–03/05...
  • Page 69 ATtiny26(L) Figure 40. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE OC1A OC1A OC1B OC1B FLOW IRQ MATCH A IRQ MATCH B IRQ (PB0) (PB1) (PB3) (PB2) TIMER INT. MASK TIMER INT. FLAG T/C CONTROL T/C CONTROL T/C CONTROL...
  • Page 70 The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is set. • Bit 2 – FOC1B: Force Output Compare Match 1B ATtiny26(L) 1477G–AVR–03/05...
  • Page 71 Writing a zero to this bit will have no effect. This bit will always read as zero. • Bit 5..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. 1477G–AVR–03/05...
  • Page 72 The Timer/Counter Output Compare Register A contains data to be continuously com- pared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A soft- ATtiny26(L) 1477G–AVR–03/05...
  • Page 73 Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and always read as zero. • Bit 2 – PCKE: PCK Enable The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchro- nous clock mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1 clock source.
  • Page 74 Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the Output Compare Register (OCR1C), and starting from $00 up again. A compare match with OC1C will set an Overflow Interrupt Flag (TOV1) after a synchronization delay following the compare event. ATtiny26(L) 1477G–AVR–03/05...
  • Page 75 ATtiny26(L) Table 35. Compare Mode Select in PWM Mode COM1x1 COM1x0 Effect on Output Compare Pins OC1x not connected. OC1x not connected. OC1x cleared on compare match. Set when TCNT1 = $01. OC1x set one prescaled cycle after compare match. Cleared when TCNT1 = $00.
  • Page 76 + 1). See the following equation: TCK1 ----------------------------------- - OCR1C + 1 Resolution shows how many bit is required to express the value in the OCR1C Register. It is calculated by following equation Resolution = log (OCR1C + 1) ATtiny26(L) 1477G–AVR–03/05...
  • Page 77 ATtiny26(L) Table 37. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency (kHz) Clock Selection CS13..CS10 OCR1C RESOLUTION (Bits) PCK/16 0101 PCK/16 0101 PCK/8 0100 PCK/8 0100 PCK/8 0100 PCK/4 0011 PCK/4 0011 PCK/4 0011 PCK/4 0011 PCK/4 0011...

  • Page 78: Watchdog Timer

    Watchdog Timer. Eight different clock cycle periods can be selected to deter- mine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny26(L) resets and executes from the Reset Vector. For timing details on the Watch- dog Reset, refer to page 34.
  • Page 79 ATtiny26(L) 1. In the same operation, write a logical one to WDCE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog.

  • Page 80: Universal Serial Interface - Usi

    The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. ATtiny26(L) 1477G–AVR–03/05...

  • Page 81: Register Descriptions

    ATtiny26(L) Register Descriptions USI Data Register – USIDR $0F ($2F) USIDR Read/Write Initial Value The USI uses no buffering of the serial register, i.e., when accessing the Data Register (USIDR) the serial register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
  • Page 82 USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the description of “Bit 6 – USIOIF: Counter Overflow Interrupt Flag” on page 81 for further details. ATtiny26(L) 1477G–AVR–03/05...
  • Page 83 ATtiny26(L) • Bit 5..4 – USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function.
  • Page 84 When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. ATtiny26(L) 1477G–AVR–03/05...

  • Page 85: Functional Descriptions

    ATtiny26(L) Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and SCK.
  • Page 86 The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle SCK (PORTB2). The loop is repeated 16 times. ATtiny26(L) 1477G–AVR–03/05...
  • Page 87 ATtiny26(L) The following code demonstrates how to use the USI module as a SPI Master with max- imum speed (fsck = fck/2): SPITransfer_Fast: USIDR,r16 r16,(1<<USIWM0)+(0<<USICS0)+(1<<USITC) r17,(1<<USIWM0)+(0<<USICS0)+(1<<USITC)+(1<<USICLK) USICR,r16 ; MSB USICR,r17 USICR,r16 USICR,r17 USICR,r16 USICR,r17 USICR,r16 USICR,r17 USICR,r16 USICR,r17 USICR,r16 USICR,r17...
  • Page 88 The clock is generated by the master by toggling the PB2 pin via the PORTB Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. ATtiny26(L) 1477G–AVR–03/05...
  • Page 89 ATtiny26(L) Figure 48. Two-wire Mode, Typical Timing Diagram 1 - 7 1 - 8 1 - 8 ADDRESS DATA DATA Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps: 1. The a start condition is generated by the master by forcing the SDA low line while the SCL line is high (A).

  • Page 90: Alternative Usi Usage

    The overflow flag and interrupt enable bit are then used for the external inter- rupt. This feature is selected by the USICS1 bit. Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. ATtiny26(L) 1477G–AVR–03/05...

  • Page 91: Analog Comparator

    ATtiny26(L) Analog Comparator The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher than the voltage on the negative pin PA7 (AIN1), the Analog Comparator Output, ACO is set (one).
  • Page 92 Comparator Interrupt on Rising Output Edge Note: 1. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATtiny26(L) 1477G–AVR–03/05...
  • Page 93 ATtiny26(L) Table 42. Analog Comparator Input Selection ACME ADEN MUX3...0 Analog Comparator Negative Input XXXX AIN1 XXXX AIN1 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 ADC8 1001 ADC9 1010 ADC10...

  • Page 94: Analog To Digital Converter

    • Sleep Mode Noise Canceler The ATtiny26(L) features a 10-bit successive approximation ADC. The ADC is con- nected to an 11-channel Analog Multiplexer which allows eight differential voltage input combinations or 11 single-ended voltage inputs constructed from seven pins from Port A and four pins from Port B.

  • Page 95: Operation

    ATtiny26(L) Figure 51. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS ADC DATA REGISTER ADC MULTIPLEXER ADC CTRL. & STATUS (ADCH/ADCL) SELECT (ADMUX) REGISTER (ADCSR) PRESCALER MUX DECODER CONVERSION LOGIC AREF SAMPLE & HOLD COMPARATOR INTERNAL 2.56 V...

  • Page 96: Prescaling And Conversion Timing

    When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Prescaling and Figure 52. ADC Prescaler Conversion Timing Reset ADEN 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE ATtiny26(L) 1477G–AVR–03/05...
  • Page 97 ATtiny26(L) The successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency from any chip clock frequency above 100 kHz.

  • Page 98: Changing Channel Or Reference Selection

    ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. ATtiny26(L) 1477G–AVR–03/05...

  • Page 99: Adc Noise Canceler Function

    ATtiny26(L) Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started within the first 125 µs after selecting a new differential channel.
  • Page 100 ADCR = 1024 * 20 * (400 - 300) / 2560 = 800 = 0x320 ADCL will thus read 0x00, and ADCH will read 0xC8. Writing zero to ADLAR right adjusts the result: ADCL = 0x20, ADCH = 0x03. ATtiny26(L) 1477G–AVR–03/05...
  • Page 101 ATtiny26(L) ADC Multiplexer Selection Register – ADMUX $07 ($27) REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write Initial Value • Bit 7, 6 – REFS1, REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 45. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
  • Page 102 ADC5 11000 ADC6 ADC5 11001 ADC8 ADC9 11010 ADC8 ADC9 11011 ADC9 ADC9 11100 ADC10 ADC9 11101 ADC10 ADC9 11110 1.18V (V 11111 0V (GND) Note: 1. For offset measurements only. See “Offset Compensation Schemes” on page 105. ATtiny26(L) 1477G–AVR–03/05...
  • Page 103 ATtiny26(L) ADC Control and Status Register – ADCSR $06 ($26) ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off.
  • Page 104 These bits represent the result from the conversion. For differential channels, this is the absolute value after gain adjustment, as indicated in Table 46 on page 102. For single ended channels, $000 represents analog ground, and $3FF represents the selected ref- erence voltage minus one LSB. ATtiny26(L) 1477G–AVR–03/05...

  • Page 105: Scanning Multiple Channels

    If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATtiny26(L) and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB.
  • Page 106 Figure 57. ADC Power Connections (MOSI/DI/SDA/OC1A) PB0 PA0 (ADC0) (MISO/DO/OC1A) PB1 PA1 (ADC1) (SCK/SCL/OC1B) PB2 PA2 (ADC2) (OC1B) PB3 PA3 (AREF) AVCC (ADC7/XTAL1) PB4 PA4 (ADC3) PA5 (ADC4) (ADC8/XTAL2) PB5 PA6 (ADC5/AIN0) (ADC9/INT0/T0) PB6 PA7 (ADC6/AIN1) (ADC10/RESET) PB7 ATtiny26(L) 1477G–AVR–03/05...

  • Page 107: Memory Programming

    Memory Programming Program and Data The ATtiny26 provides two Lock bits which can be left unprogrammed (“1”) or can be Memory Lock Bits programmed (“0”) to obtain the additional features listed in Table 49. The Lock bits can only be erased to “1” with the Chip Erase command.

  • Page 108: Fuse Bits

    Fuse Bits The ATtiny26 has two Fuse bytes. Table 50 and Table 51 describe briefly the functional- ity of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.

  • Page 109: Signature Bytes

    Parallel Programming This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny26. Pulses are Parameters, Pin assumed to be at least 250 ns unless otherwise noted.
  • Page 110 1. The pin is used for two different control signals. In the description below, normally only one of the signals is referred. E.g., “give BS1 a positive pulse” equals “give PAGEL/BS1 a positive pulse”. Table 55. Pin Values used to Enter Programming Mode Symbol Value PAGEL/BS1 Prog_enable[3] XA1/BS2 Prog_enable[2] Prog_enable[1] Prog_enable[0] ATtiny26(L) 1477G–AVR–03/05...
  • Page 111 ATtiny26(L) Table 56. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle Note: 1.

  • Page 112: Parallel Programming

    EESAVE Fuse is programmed) and Flash after a Chip Erase. • Address high byte needs only be loaded before programming or reading a new 256- word window in Flash or 256-byte EEPROM. This consideration also applies to Signature bytes reading. ATtiny26(L) 1477G–AVR–03/05...
  • Page 113 ATtiny26(L) Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
  • Page 114 Figure 59. Addressing the Flash which is Organized in Pages PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 52 on page 109. ATtiny26(L) 1477G–AVR–03/05...
  • Page 115 ATtiny26(L) Figure 60. Programming the Flash Waveforms ADDR. LOW DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH ADDR. HIGH DATA XA1/BS2 PAGEL/BS1 XTAL1 RDY/BSY RESET +12V Note: 1. “XX” is don’t care. The letters refer to the programming description above.
  • Page 116 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 and BS2 to “0”. 4. Give WR a negative pulse and wait for RDY/BSY to go high. ATtiny26(L) 1477G–AVR–03/05...
  • Page 117 ATtiny26(L) Programming the Fuse High The algorithm for programming the Fuse high bits is as follows (refer to “Programming Bits the Flash” on page 113 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
  • Page 118 3. Set OE to “0” and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. Parallel Programming Figure 64. Parallel Programming Timing, Including some General Timing Characteristics Requirements XLWL XHXL XTAL1 DVXH XLDX Data & Contol (DATA, XA0, XA1/BS2 PAGEL/BS1) BVWL WLBX WLWH WLRL RDY/BSY WLRH ATtiny26(L) 1477G–AVR–03/05...
  • Page 119 ATtiny26(L) Figure 65. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS LOAD DATA LOAD DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (LOW BYTE) (HIGH BYTE) XLXH XLXH XLXH XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte)
  • Page 120 OE Low to DATA Valid OLDV OE High to DATA Tri-stated OHDZ Notes: is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock WLRH bits commands. 2. t is valid for the Chip Erase command. WLRH_CE ATtiny26(L) 1477G–AVR–03/05...

  • Page 121: Serial Downloading

    ATtiny26(L) Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
  • Page 122 SPI Serial Programming When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure 68, Figure 69, and Table 69 for timing details.
  • Page 123 ATtiny26(L) Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written.
  • Page 124 0000 00bb oooo oooo Note: a = address high bits b = address low bits H = 0 – Low byte, 1 – High Byte o = data out i = data in x = don’t care ATtiny26(L) 1477G–AVR–03/05...
  • Page 125 ATtiny26(L) Serial Programming Figure 69. Serial Programming Timing Characteristics MOSI SLSH OVSH SHOX SHSL MISO SLIV Table 62. Serial Programming Characteristics, T = -40°C to 85°C, V = 2.7V - 5.5V (Unless Otherwise Noted) Symbol Parameter Units Oscillator Frequency (V = 2.7 - 5.5 V)

  • Page 126: Electrical Characteristics

    (Ports A, B) = -10 mA, V = 3V Input Leakage V, pin low µA Current I/O Pin (absolute value) Input Leakage V, pin high µA Current I/O Pin (absolute value) Reset Pull-up Resistor kΩ I/O Pin Pull-up Resistor kΩ ATtiny26(L) 1477G–AVR–03/05...
  • Page 127 ATtiny26(L) = -40°C to 85°C, V = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 1 MHz, V = 3V 0.70 ATtiny26 Active 4 MHz, V = 3V ATtiny26 Active 8 MHz, V...

  • Page 128: External Clock Drive Waveforms

    1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. ATtiny26(L) 1477G–AVR–03/05...

  • Page 129: Adc Characteristics

    ATtiny26(L) ADC Characteristics Table 65. ADC Characteristics, Single Ended Channels, T = -40°C to 85°C Symbol Parameter Condition Units Resolution Single Ended Conversion Bits Single Ended Conversion = 4V, V = 4V ADC clock = 200 kHz Single Ended Conversion...
  • Page 130 AVCC - 0.5 Input Voltage Input Differential Voltage /Gain DIFF ADC Conversion Output 1023 Input Bandwidth Internal Voltage Reference Reference Input Resistance kΩ Analog Input Resistance MΩ Notes: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. ATtiny26(L) 1477G–AVR–03/05...

  • Page 131: Attiny26 Typical Characteristics

    ATtiny26(L) ATtiny26 Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source.
  • Page 132 1 - 20 MHz 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) Figure 73. Active Supply Current vs. V (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 133 ATtiny26(L) Figure 74. Active Supply Current vs. V (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 85 °C 25 °C -40 °C Figure 75. Active Supply Current vs. V (Internal RC Oscillator, 2 MHz) ACTIVE SUPPLY CURRENT vs.
  • Page 134 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 25 °C 85 °C -40 °C Figure 77. Active Supply Current vs. V (PLL Oscillator) ACTIVE SUPPLY CURRENT vs. V PLL OSCILLATOR -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 135 ATtiny26(L) Figure 78. Active Supply Current vs. V (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 25 °C Idle Supply Current Figure 79. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz...
  • Page 136 1 - 20 MHz 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) Figure 81. Idle Supply Current vs. V (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 137 ATtiny26(L) Figure 82. Idle Supply Current vs. V (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz -40 °C 25 °C 85 °C Figure 83. Idle Supply Current vs. V (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs.
  • Page 138 IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 25 °C 85 °C -40 °C Figure 85. Idle Supply Current vs. V (PLL Oscillator) IDLE SUPPLY CURRENT vs. V PLL OSCILLATOR 25 °C 85 °C -40 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 139 ATtiny26(L) Figure 86. Idle Supply Current vs. V (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 25 °C Power-down Supply Current Figure 87. Power-down Supply Current vs. V (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 85 °C...
  • Page 140 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 85 °C 25 °C -40 °C Standby Supply Current Figure 89. Standby Supply Current vs. V (455 kHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 455 kHz RESONATOR, WATCHDOG TIMER DISABLED ATtiny26(L) 1477G–AVR–03/05...
  • Page 141 ATtiny26(L) Figure 90. Standby Supply Current vs. V (1 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 1 MHz RESONATOR, WATCHDOG TIMER DISABLED Figure 91. Standby Supply Current vs. V (2 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 2 MHz RESONATOR, WATCHDOG TIMER DISABLED 1477G–AVR–03/05...
  • Page 142 (2 MHz XTAL, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 2 MHz XTAL, WATCHDOG TIMER DISABLED Figure 93. Standby Supply Current vs. V (4 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 4 MHz RESONATOR, WATCHDOG TIMER DISABLED ATtiny26(L) 1477G–AVR–03/05...
  • Page 143 ATtiny26(L) Figure 94. Standby Supply Current vs. V (4 MHz XTAL, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 4 MHz XTAL, WATCHDOG TIMER DISABLED Figure 95. Standby Supply Current vs. V (6 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 1477G–AVR–03/05...
  • Page 144 6 MHz XTAL, WATCHDOG TIMER DISABLED Pin Pull-up Figure 97. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 145 ATtiny26(L) Figure 98. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C Figure 99. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5V) RESET PULL-UP RESISTOR CURRENT vs.
  • Page 146 -40 °C 25 °C 85 °C RESET Pin Driver Strength Figure 101. I/O Pin Source Current vs. Output Voltage (V = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 147 ATtiny26(L) Figure 102. I/O Pin Source Current vs. Output Voltage (V = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V -40 °C 25 °C 85 °C Figure 103. I/O Pin Sink Current vs. Output Voltage (V = 5V) I/O PIN SINK CURRENT vs.
  • Page 148 25 °C 85 °C Figure 105. Reset Pin as I/O – Source Current vs. Output Voltage (V = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 149 ATtiny26(L) Figure 106. Reset Pin as I/O – Source Current vs. Output Voltage (V = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V -40 °C 25 °C 85 °C Figure 107. Reset Pin as I/O –Sink Current vs. Output Voltage (V = 5V) RESET PIN AS I/O - SINK CURRENT vs.
  • Page 150 Pin Thresholds and Figure 109. I/O Pin Input Threshold Voltage vs. V , I/O Pin Read as “1”) Hysteresis I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' -40 °C 85 °C 25 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 151 ATtiny26(L) Figure 110. I/O Pin Input Threshold Voltage vs. V , I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' -40 °C 25 °C 85 °C Figure 111. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs.
  • Page 152 Figure 113. Reset Pin as I/O – Input Threshold Voltage vs. V , Reset Pin Read as “0”) RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. V VIL, RESET PIN READ AS '0' -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 153 ATtiny26(L) Figure 114. Reset Pin as I/O – Pin Hysteresis vs. V RESET PIN AS I/O - PIN HYSTERESIS vs. V 85°C -40°C 25°C Figure 115. Reset Input Threshold Voltage vs. V , Reset Pin Read as “1”) RESET INPUT THRESHOLD VOLTAGE vs. V VIH, RESET PIN READ AS '1' -40 °C...
  • Page 154 RESET INPUT THRESHOLD VOLTAGE vs. V VIL, RESET PIN READ AS '0' 85 °C 25 °C -40 °C Figure 117. Reset Input Pin Hysteresis vs. V RESET INPUT PIN HYSTERESIS vs. V -40 °C 0.45 0.35 0.25 25 °C 0.15 85 °C 0.05 ATtiny26(L) 1477G–AVR–03/05...
  • Page 155 ATtiny26(L) BOD Thresholds and Analog Figure 118. BOD Thresholds vs. Temperature (BOD Level is 4.0V) Comparator Offset BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V Rising V Falling V Temperature (C) Figure 119. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs.
  • Page 156 Figure 121. Analog Comparator Offset Voltage vs. Common Mode Voltage (V = 5.0V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 0.009 0.008 0.007 0.006 0.005 -40°C 0.004 25°C 0.003 85°C 0.002 0.001 Common Mode Voltage (V) ATtiny26(L) 1477G–AVR–03/05...
  • Page 157 ATtiny26(L) Figure 122. Analog Comparator Offset Voltage vs. Common Mode Voltage (V = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 0.009 0.008 0.007 0.006 0.005 0.004 -40°C 25°C 0.003 85°C 0.002 0.001 Common Mode Voltage (V) Internal Oscillator Speed Figure 123.
  • Page 158 Figure 124. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.0V 3.5V 2.7V (˚C) Figure 125. Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 159 ATtiny26(L) Figure 126. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 17.5 15.5 13.5 11.5 OSCCAL VALUE Figure 127. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.0V...
  • Page 160 Figure 128. Calibrated 4 MHz RC Oscillator Frequency vs. V CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. V -40 °C 25 °C 85 °C Figure 129. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE OSCCAL VALUE ATtiny26(L) 1477G–AVR–03/05...
  • Page 161 ATtiny26(L) Figure 130. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.15 2.05 1.95 5.0V 3.5V 1.85 2.7V 1.75 (˚C) Figure 131. Calibrated 2 MHz RC Oscillator Frequency vs. V CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. V 2.15...
  • Page 162 Figure 132. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE OSCCAL VALUE Figure 133. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 1.02 0.98 5.0V 0.96 3.5V 0.94 2.7V 0.92 ATtiny26(L) 1477G–AVR–03/05...
  • Page 163 ATtiny26(L) Figure 134. Calibrated 1 MHz RC Oscillator Frequency vs. V CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. V 1.05 -40°C 25°C 85°C 0.95 0.85 Figure 135. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE OSCCAL VALUE 1477G–AVR–03/05...
  • Page 164 BROWNOUT DETECTOR CURRENT vs. V 0.035 0.03 0.025 -40 °C 0.02 25 °C 85 °C 0.015 0.01 0.005 Figure 137. ADC Current vs. V (AREF = AV ADC CURRENT vs. V AREF = AVCC -40 °C 25 °C 85 °C ATtiny26(L) 1477G–AVR–03/05...
  • Page 165 ATtiny26(L) Figure 138. AREF External Reference Current vs. V AREF EXTERNAL REFERENCE CURRENT vs. VCC -40 °C 25 °C 85 °C Figure 139. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 85 °C 25 °C -40 °C 1477G–AVR–03/05...
  • Page 166 Reset and Reset Pulsewidth (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. V 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) ATtiny26(L) 1477G–AVR–03/05...
  • Page 167 ATtiny26(L) Figure 142. Reset Supply Current vs. V (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. V 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) Figure 143.

  • Page 168: Register Summary

    ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 $06 ($26) ADCSR ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 $05 ($25) ADCH ADC Data Register High Byte $04 ($24) ADCL ADC Data Register Low Byte … Reserved $00 ($20) Reserved ATtiny26(L) 1477G–AVR–03/05...

  • Page 169: Instruction Set Summary

    ATtiny26(L) Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add Two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry Two Registers Z,C,N,V,H Rdh:Rdl ←...
  • Page 170 Clear T in SREG H ← 1 Set Half-carry Flag in SREG H ← 0 Clear Half-carry Flag in SREG No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None ATtiny26(L) 1477G–AVR–03/05...

  • Page 171: Ordering Information

    32M1-A Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc- tive).

  • Page 172: Packaging Information

    Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 0.203 – 0.356 – – 10.922 0.000 – 1.524 2.540 TYP 1/12/04 TITLE DRAWING NO. REV. 2325 Orchard Parkway 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual 20P3 San Jose, CA 95131 Inline Package (PDIP) ATtiny26(L) 1477G–AVR–03/05...

  • Page 173: 173

    ATtiny26(L) Top View End View COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL NOTE 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.4961 0.5118 0.2914 0.2992 Side View 0.3940 0.4190 0.0160 0.050 0.050 BSC Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.

  • Page 174: 32M1-A

    0.20 – – 8/19/04 TITLE DRAWING NO. REV. 2325 Orchard Parkway 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 32M1-A San Jose, CA 95131 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) ATtiny26(L) 1477G–AVR–03/05...

  • Page 175: Errata

    ATtiny26(L) Errata ATtiny26, all revisions No errata. 1477G–AVR–03/05...

  • Page 176: Datasheet Revision History

    Figure 122 in “BOD Thresholds and Analog Comparator Offset” on page 155. Updated Figure 117 and Figure 118. 9. Removed LPM Rd, Z+ from “Instruction Set Summary” on page 169. This instruction is not supported in ATtiny26. Changes from Rev. 1. Updated “Packaging Information” on page 172.

  • Page 177: Changes From Rev. 1477B-04/02 To Rev. 1477C-09/02

    12. Updated “ADC Characteristics” on page 129 and added Table 66, “ADC Char- acteristics, Differential Channels, T = -40°C to 85°C,” on page 130. 13. Updated “ATtiny26 Typical Characteristics” on page 131. 14. Added LPM Rd, Z and LPM Rd, Z+ in “Instruction Set Summary” on page 169. Changes from Rev.

  • Page 178: Table Of Contents

    ATtiny26(L) Table of Contents Features....................1 Pin Configuration................. 2 Description ................... 3 Block Diagram ...................... 4 Pin Descriptions....................5 About Code Examples................. 5 AVR CPU Core ..................6 Architectural Overview..................6 General Purpose Register File ................7 ALU – Arithmetic Logic Unit.................. 8 Status Register –...
  • Page 179 Changing Channel or Reference Selection ............98 ADC Noise Canceler Function................99 ADC Conversion Result..................99 Scanning Multiple Channels ................105 ADC Noise Canceling Techniques ..............105 Offset Compensation Schemes ................ 105 Memory Programming..............107 Program and Data Memory Lock Bits............... 107 ATtiny26(L) 1477G–AVR–03/05...
  • Page 180 Absolute Maximum Ratings*................126 DC Characteristics.................... 126 External Clock Drive Waveforms ..............128 External Clock Drive ..................128 ADC Characteristics ..................129 ATtiny26 Typical Characteristics ........... 131 Register Summary ................168 Instruction Set Summary ..............169 Ordering Information............... 171 Packaging Information ..............172 20P3 .........................
  • Page 181 ATtiny26(L) 1477G–AVR–03/05...
  • Page 182 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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