Serial Downloading - Atmel ATtiny25 Manual

21.6

Serial Downloading

21.6.1 Serial Programming Algorithm
ATtiny25/45/85
138
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 21-1. Serial Programming and Verify
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
CLKI pin.
Table 21-8. Pin Mapping Serial Programming
Symbol
MOSI
MISO
SCK
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See
Figure 21-2 and Figure 21-3
(1)
MOSI
MISO
SCK
RESET
GND
Pins I/O
PB0 I
PB1 O
PB2 I
< 12 MHz, 3 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
for timing details.
Table 21-8 on page
+4.5 - 5.5V
VCC
Description
Serial Data in
Serial Data out
Serial Clock
>= 12 MHz
ck
>= 12 MHz
ck
138, the pin
7598H–AVR–07/09