Prescaling And Conversion Timing - Atmel ATtiny25 Manual

18.4

Prescaling and Conversion Timing

ATtiny25/45/85
114
Figure 18-2. ADC Auto Trigger Logic
ADTS[2:0]
ADIF
SOURCE 1
.
.
.
.
SOURCE n
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
Figure 18-3. ADC Prescaler
ADEN
START
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is
not recommended to use a higher input clock frequency than 1 MHz.
ADATE
EDGE
DETECTOR
Reset
7-BIT ADC PRESCALER
CK
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
PRESCALER
START CLK
CONVERSION
LOGIC
7598H–AVR–07/09
ADC