Atmel AVR ATtiny15L Manual
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Atmel AVR ATtiny15L Manual

Microcontroller with 1k byte flash
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Features
•
High-performance, Low-power AVR
•
Advanced RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
•
Non-volatile Program and Data Memories
– 1K Byte In-System Programmable Flash Program Memory
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program Data Security
•
Peripheral Features
– Interrupt and Wake-up on Pin Change
– Two 8-bit Timer/Counters with Separate Prescalers
– One 150 kHz, 8-bit High-speed PWM Output
– 4-channel 10-bit ADC
One Differential Voltage Input with Optional Gain of 20x
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
•
Special Microcontroller Features
– In-System Programmable via SPI Port
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal, Calibrated 1.6 MHz Tunable Oscillator
– Internal 25.6 MHz Clock Generator for Timer/Counter
– External and Internal Interrupt Sources
– Low-power Idle and Power-down Modes
•
Power Consumption at 1.6 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down: < 1 µA
•
I/O and Packages
– 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines
•
Operating Voltages
– 2.7V - 5.5V
•
Internal 1.6 MHz System Clock
Pin Configuration
(RESET/ADC0) PB5
(ADC3) PB4
(ADC2) PB3
®
8-bit Microcontroller
PDIP/SOIC
1
8
VCC
2
7
PB2 (ADC1/SCK/T0/INT0)
3
6
PB1 (AIN1/MISO/OC1A)
GND
4
5
PB0 (AIN0/AREF/MOSI)
8-bit
Microcontroller
with 1K Byte
Flash
ATtiny15L
Not recommended for new
design
Rev. 1187H–AVR–09/07
1

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Summary of Contents for Atmel AVR ATtiny15L

  • Page 1 Features ® • High-performance, Low-power AVR 8-bit Microcontroller • Advanced RISC Architecture – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories –...
  • Page 2 Power-saving modes. The device is manufactured using Atmel’s high-density, Non-volatile memory technol- ogy. By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a powerful microcontroller that provides a highly flexible and cost-efficient solution to many embedded control applications.

  • Page 3: Block Diagram

    ATtiny15L Block Diagram Figure 1. The ATtiny15L Block Diagram 8-BIT DATA BUS TUNABLE INTERNAL INTERNAL OSCILLATOR OSCILLATOR PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL PROGRAM HARDWARE REGISTER FLASH STACK INSTRUCTION MCU STATUS REGISTER REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION TIMER/...

  • Page 4: Pin Descriptions

    Pin Descriptions Supply voltage pin. Ground pin. Port B (PB5..PB0) Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse and the special function associated with this pin is External Reset.

  • Page 5: Attiny15L Architectural Overview

    ATtiny15L ATtiny15L The fast-access Register File concept contains 32 x 8-bit general purpose working reg- isters with a single-clock-cycle access time. This means that during one single clock Architectural cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output Overview from the Register File, the operation is executed, and the result is stored back in the Register File –...

  • Page 6: The General Purpose Register File

    A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep- arate Interrupt Vector in the Interrupt Vector table at the beginning of the program memory.

  • Page 7: The Program And Data Addressing Modes

    ATtiny15L The Program and Data The ATtiny15L AVR RISC Microcontroller supports powerful and efficient addressing Addressing Modes modes. This section describes the various addressing modes supported in the ATtiny15L. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.
  • Page 8 Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 7. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. “n” is the destination or source register address.

  • Page 9: Subroutine And Interrupt Hardware Stack

    ATtiny15L Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), and LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Subroutine and Interrupt The ATtiny15L uses a 3-level-deep Hardware Stack for subroutines and interrupts.
  • Page 10 Figure 11. Single Cycle ALU Operation System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back I/O Memory The I/O space definition of the ATtiny15L is shown in Table 2. Table 2. ATtiny15L I/O Space Address Hex Name Function...
  • Page 11 ATtiny15L Table 2. ATtiny15L I/O Space (Continued) Address Hex Name Function ADCSR ADC Control and Status Register ADCH ADC Data Register High ADCL ADC Data Register Low Note: 1. Reserved and unused locations are not shown in the table. All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space.

  • Page 12: Reset And Interrupt Handling

    • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result after the different arithmetic and logic opera- tions.
  • Page 13 ATtiny15L The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address Labels Code Comments $000 rjmp RESET ; Reset handler $001 rjmp EXT_INT0 ; IRQ0 handler $002 rjmp PIN_CHANGE ; Pin change handler $003 rjmp TIM1_CMP ;...
  • Page 14 Figure 12. Reset Logic DATA BUS MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL Reset Circuit Watchdog Timer Watchdog Oscillator Delay Counters Tunable Internal Oscillator TIMEOUT CKSEL[1:0] Table 4. Reset Characteristics (V = 5.0V) Symbol Parameter Condition Units BOD disabled...
  • Page 15 ATtiny15L Table 5. Reset Delay Selections Start-up Time, Start-up Time, Recommended BODEN CKSEL [1:0] at V = 2.7V at V = 5.0V Usage TOUT TOUT BOD disabled, 256 ms + 18 CK 64 ms + 18 CK slowly rising power BOD disabled, 256 ms + 18 CK 64 ms + 18 CK...
  • Page 16 Figure 13. “MCU Start-up, RESET Tied to V RESET TOUT TIME-OUT INTERNAL RESET Figure 14. MCU Start-up, RESET Extended Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An External Reset is generated by a low-level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running.
  • Page 17 ATtiny15L Brown-out Detection ATtiny15L has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V decreases below the trigger level, the Brown-out Reset is immediately activated. When V increases above the trigger level, the Brown-out Reset is deactivated after a delay.

  • Page 18: Internal Voltage Reference

    MCU Status Register – The MCU Status Register provides information on which reset source caused an MCU MCUSR Reset. – – – – WDRF BORF EXTRF PORF MCUSR Read/Write Initial Value See Bit Description • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero.

  • Page 19: Interrupt Handling

    ATtiny15L Interrupt Handling The ATtiny15L has two 8-bit Interrupt Mask Control Registers: GIMSK (General Inter- rupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled. The user software can set the I-bit (one) to enable interrupts. The I- bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
  • Page 20 The corresponding interrupt of External Interrupt Request 0 is executed from Program memory address $001. See also “External Interrupts.” • Bit 5 – PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt on pin change is enabled.
  • Page 21 ATtiny15L vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 5..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. •...
  • Page 22 • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 (Tim er/Co un ter0 Ove rflow Inte rrup t En able) an d TO V0 a re set (o ne) , th e Timer/Counter0 Overflow interrupt is executed.

  • Page 23: Sleep Modes

    ATtiny15L • Bits 4, 3 – SM1, SM0: Sleep Mode Select Bits 1 and 0 These bits select between the three available sleep modes, as shown in Table 7. Table 7. Sleep Modes Sleep Mode Idle mode ADC Noise Reduction mode Power-down mode Reserved For details, refer to “Sleep Modes”...

  • Page 24: Tuneable Internal Rc Oscillator

    ADC Noise Reduction Mode When the SM1/SM0 bits are “01”, the SLEEP instruction forces the MCU into the ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupt pin, pin change interrupt and the Watchdog (if enabled) to continue operating. Please note that the clock system including the PLL is also active in the ADC Noise Reduction mode.

  • Page 25: The Timer/Counter0 Prescaler

    ATtiny15L Timer/Counters The ATtiny15L provides two general purpose 8-bit Timer/Counters. The Timer/Counters have sepa ra te pr es caling selection from separate 10-bit prescalers. The Timer/Counter0 uses internal clock (CK) as the clock time base. The Timer/Counter1 may use either the internal clock (CK) or the fast peripheral clock (PCK) as the clock time base.

  • Page 26: The 8-Bit Timer/Counter0

    The Special Function IO Register – SFIOR – – – – – FOC1A PSR1 PSR0 SFIOR Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 2 – FOC1A: Force Output Compare 1A Writing a logical “1”...
  • Page 27 ATtiny15L Figure 20. Timer/Counter0 Block Diagram T/C CLK SOURCE The Timer/Counter0 Control Register – TCCR0 – – – – – CS02 CS01 CS00 TCCR0 Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. •...

  • Page 28: The 8-Bit Timer/Counter1

    The Timer Counter 0 – TCNT0 TCNT0 Read/Write Initial Value The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation. The 8-bit Timer/Counter1 This module features a high-resolution and a high-accuracy usage with the lower pres- caling opportunities.
  • Page 29 ATtiny15L The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1B, as the data source to be compared with the Timer/Counter1 contents. In Normal mode the Output Compare function is operational with OCR1A only, and the Output Compare function includes optional clearing of the counter on compare match, and action on the Output Compare pin (PB1) (OC1A).
  • Page 30 • Bits 3, 2, 1, 0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 11. Timer/Counter1 Prescale Select CS13 CS12 CS11 CS10...
  • Page 31 ATtiny15L Timer/Counter1 Output Compare RegisterA – OCR1A OCR1A Read/Write Initial Value The Output Compare Register 1A is an 8-bit read/write register. The Timer/Counter Output Compare Register 1A contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match occurs only if Timer/Counter1 counts to the OCR1A value.
  • Page 32 Figure 22. Effects of Unsynchronized OCR Latching Compare Value Changes Counter Value Compare Value PWM Output OC1A Synchronized OC1A Latch Compare Value Changes Counter Value Compare Value PWM Output OC1A Glitch Unsynchronized OC1A Latch During the time between the write and the latch operation, a read from OCR1A will read the contents of the temporary location.
  • Page 33 ATtiny15L The frequency of the PWM will be Timer Clock Frequency divided by OCR1B value + 1. Table 14. Timer/Counter1 Clock Prescale Select Clock Selection OCR1B PWM Frequency 10 kHz PCK/8 20 kHz PCK/4 30 kHz PCK/4 40 kHz PCK/2 50 kHz PCK/2 60 kHz...

  • Page 34: The Watchdog Timer

    The Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value at V = 5V. See “Typical Characteristics” on page 66 for typical values at other V levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16 to 2,048 ms, as shown in Table 15.
  • Page 35 ATtiny15L 1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog.
  • Page 36 EEPROM Read/Write The EEPROM Access Registers are accessible in the I/O space. Access The write access time is in the range of 4.6 - 8.2 ms, depending on the frequency of the calibrated RC Oscillator. See Table 16 for details. A self-timing function however, lets the user software detect when the next byte can be written.
  • Page 37 ATtiny15L The EEPROM Control Register – EECR – – – – EERIE EEMWE EEWE EERE EECR Read/Write Initial value • Bit 7..4 – RES: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. •...

  • Page 38: Preventing Eeprom Corruption

    The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O Registers, the write operation will be interrupted and the result is undefined. The calibrated oscillator is used to time EEPROM.

  • Page 39: The Analog Comparator

    ATtiny15L The Analog The Analog Comparator compares the input values on the positive pin PB0 (AIN0) and negative pin PB1 (AIN1). When the voltage on the positive pin PB0 (AIN0) is higher than Comparator the voltage on the negative pin PB1 (AIN1), the Analog Comparator Output (ACO) is set (one).
  • Page 40 • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana- log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. •...

  • Page 41: The Analog-To-Digital Converter, Analog Multiplexer, And Gain Stages

    ATtiny15L The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages Features • 10-bit Resolution • ±2 LSB Absolute Accuracy • 0.5 LSB Integral Non-linearity • Optional Offset Cancellation • 65 - 260 µs Conversion Time • Up to 15 kSPS • 4 Multiplexed Single-ended Input Channels •...

  • Page 42: Operation

    Figure 25. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS ADC DATA REGISTER ADC MULTIPLEXER ADC CTRL. & STATUS (ADCH/ADCL) SELECT (ADMUX) REGISTER (ADCSR) PRESCALER MUX DECODER CONVERSION LOGIC AREF SAMPLE & HOLD COMPARATOR INTERNAL 2.56 V 10-BIT DAC REFERENCE SINGLE ENDED / DIFFERENTIAL SELECTION...

  • Page 43: Prescaling And Conversion Timing

    ATtiny15L mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR bit in ADCSR selects between the two available modes. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering Power-saving sleep modes.
  • Page 44 the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle.
  • Page 45 ATtiny15L Figure 28. ADC Timing Diagram, Single Conversion Next Extended Conversion Conversion Cycle Number ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Conversion MUX and REFS Sample & Hold Update Complete Update Figure 29.

  • Page 46: Adc Noise Canceler Function

    ADC Noise Canceler The ADC features a noise canceler that enables conversion during ADC Noise Reduc- Function tion mode (see “Sleep Modes” on page 23) to reduce noise induced from the CPU core and other I/O peripherals. If other I/O peripherals must be active during conversion, this mode works equivalently for Idle mode.
  • Page 47 ATtiny15L • Bits 4..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel and Gain Selection Bits 2..0 The value of these bits selects which analog input is connected to the ADC. In case of differential input (PB3 - PB4), gain selection is also made with these bits.
  • Page 48 channel must be selected before entering Free Running mode. Selecting an active channel after entering Free Running mode may result in undefined operation from the ADC. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the Data Registers are updated.
  • Page 49 ATtiny15L The ADC Data Register – ADCL and ADCH ADLAR = 0 – – – – – – ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial Value ADLAR = 1 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3...

  • Page 50: Adc Noise-Canceling Techniques

    ADC Noise-canceling Digital circuitry inside and outside the ATtiny15L generates EMI, which might affect the Techniques accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATtiny15L and all analog components in the application should have a separate analog ground plane on the PCB.

  • Page 51: Unconnected Pins

    ATtiny15L I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
  • Page 52 The Port B Input Pins Address – PINB – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write Initial Value The Port B Input Pins address (PINB) is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the pins are read.
  • Page 53 ATtiny15L In Normal mode, this pin can serve as the external counter clock input. See the Timer/Counter0 description for further details. If external Timer/Counter clocking is selected, activity on this pin will clock the counter even if it is configured as an output. •...

  • Page 54: Memory Programming

    Programming mode caused by drive contention on PB0 and/or PB5. Signature Bytes All Atmel microcontrollers have a three-byte signature code that identifies the device. The three bytes reside in a separate address space, and for the ATtiny15L they are: 1. $000 : $1E (indicates manufactured by Atmel).

  • Page 55: Calibration Byte

    OSCCAL Register. Programming the Flash Atmel’s ATtiny15L offers 1K byte of In-System Reprogrammable Flash Program mem- ory and 64 bytes of in-System Reprogrammable EEPROM Data memory. The ATtiny15L is shipped with the On-chip Flash program and EEPROM data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed.

  • Page 56: High-Voltage Serial Programming Algorithm

    High-voltage Serial To program and verify the ATtiny15L in the High-voltage Serial Programming mode, the Programming Algorithm following sequence is recommended (See instruction formats in Table 25): 1. Power-up sequence: Apply 4.5 - 5.5V between V and GND. Set PB5 and PB0 to “0” and wait at least 30 µs.
  • Page 57 ATtiny15L Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.4 Operation Remarks 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 0_0000_0000_00 Wait after Instr.3 until PB2 Chip Erase 0_0100_1100_00 0_0110_0100_00 0_0110_1100_00 0_0100_1100_00 goes high for the Chip Erase cycle to finish.
  • Page 58 Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L (Continued) Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.4 Operation Remarks 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 Read Lock Reading 2, 1 = “0” means the 0_0100_1100_00 0_0111_1000_00 0_0111_1100_00 Bits Lock bit is programmed x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_21xx_xx 0_0000_1000_00...

  • Page 59: High-Voltage Serial Programming Characteristics

    ATtiny15L High-voltage Serial Figure 32. High-voltage Serial Programming Timing Programming VALID SDI (PB0), SII (PB1) Characteristics IVSH SHIX SHSL SLSH SCI (PB3) SDO (PB2) SHOV Internal CK Table 26. High-voltage Serial Programming Characteristics, T = 25°C ± 10%, = 5.0V ± 10% (unless otherwise noted) Symbol Parameter Units...
  • Page 60 The device is clocked from the internal clock at the uncalibrated minimum frequency (0.8 - 1.6 MHz). The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles Low-voltage Serial When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK.

  • Page 61: Data Polling

    ATtiny15L Data Polling When a byte is being programmed into the Flash or EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
  • Page 62 Table 27. Low-voltage Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable Enable Serial Programming while 1010 1100 0101 0011 xxxx xxxx xxxx xxxx RESET is low. Chip Erase Chip Erase Flash and EEPROM 1010 1100 100x xxxx xxxx xxxx...

  • Page 63: Low-Voltage Serial Programming Characteristics

    ATtiny15L Low-voltage Serial Figure 35. Low-voltage Serial Programming Timing Programming Characteristics MOSI SLSH OVSH SHOX SHSL MISO SLIV Table 28. Low-voltage Serial Programming Characteristics, T = -40°C to 85°C, = 2.7 - 5.5V (Unless Otherwise Noted) Symbol Parameter Units RC Oscillator Frequency (V = 2.7 - 5.5V) CLCL RC Oscillator Period (V...

  • Page 64: Electrical Characteristics

    Electrical Characteristics Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or Voltage on Any Pin Except RESET other conditions beyond those indicated in the...
  • Page 65 ATtiny15L DC Characteristics (Continued) = -40°C to 85°C, V = 2.7V to 5.5V Symbol Parameter Condition Units Analog Comparator = 5V 40.0 ACIO Input Offset Voltage Analog Comparator = 5V -50.0 50.0 ACLK Input Leakage Current Analog Comparator = 2.7V 750.0 ACID Initialization Delay...

  • Page 66: Typical Characteristics

    Typical The following charts show typical behavior. These data are characterized but not tested. All current consumption measurements are performed with all I/O pins configured as Characteristics inputs and with internal pull-ups enabled. The current consumption is a function of several factors such as: Operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature.
  • Page 67 ATtiny15L Figure 37. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.6MHz INTERNAL RC OSCILLATOR T = 85 ˚ T = 25 ˚ Figure 38. Calibrated Internal RC Oscillator Frequency vs. V Relative Calibrated RC Oscillator Frequency vs. Operating Voltage 1.02 T = 25 ˚...
  • Page 68 Figure 39. Bandgap Voltage vs. V BANDGAP VOLTAGE vs. V MEASURED WITH ANALOG COMPARATOR 1.301 T = 25 ˚ T = 45 ˚ 1.299 T = 70 ˚ 1.298 T = 85 ˚ 1.297 1.296 1.295 1.294 1.293 1.292 Figure 40. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs.
  • Page 69 ATtiny15L Figure 41. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 42. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25...
  • Page 70 Figure 43. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 T = 25 ˚ 1200 T = 85 ˚ 1000 V (V) Note: 1. Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 44.
  • Page 71 ATtiny15L Figure 45. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 46. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚...
  • Page 72 Figure 47. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 48. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚...
  • Page 73 ATtiny15L Figure 49. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 50. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚...
  • Page 74 Figure 51. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12 0.08 0.06 0.04 0.02 ATtiny15L 1187H–AVR–09/07...

  • Page 75: Attiny15L Register Summary

    ATtiny15L ATtiny15L Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page SREG page 11 Reserved Reserved GIMSK INT0 PCIE page 19 GIFR INTF0 PCIF page 20 TIMSK OCIE1A TOIE1 TOIE0 page 20...

  • Page 76: Attiny15L Instruction Set Summary

    ATtiny15L Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add Two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry Two Registers Z,C,N,V,H Rd ←...
  • Page 77 ATtiny15L ATtiny15L Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks I/O(P,b) ← 0 P, b Clear Bit in I/O Register None Rd(n+1) ← Rd(n), Rd(0) ← 0 Logical Shift Left Z,C,N,V Rd(n) ← Rd(n+1), Rd(7) ← 0 Logical Shift Right Z,C,N,V Rd(0) ←...

  • Page 78: Ordering Information

    Ordering Information Power Supply Speed (MHz) Ordering Code Package Operation Range ATtiny15L-1PC Commercial ATtiny15L-1PU (0°C to 70°C) ATtiny15L-1SC ATtiny15L-1SU 2.7 - 5.5V ATtiny15L-1PI Industrial ATtiny15L-1PU (-40°C to 85°C) ATtiny15L-1SI ATtiny15L-1SU Note: 1. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
  • Page 79 ATtiny15L Package Type 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 1187H–AVR–09/07...

  • Page 80: Packaging Information

    Packaging Information Top View End View COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL NOTE A2 A 0.210 0.115 0.130 0.195 0.014 0.018 0.022 0.045 0.060 0.070 0.030 0.039 0.045 0.008 0.010 0.014 0.355 0.365 0.400 0.005 0.300 0.310 0.325 4 PLCS 0.240 0.250...

  • Page 81: Top View

    ATtiny15L θ θ TOP VIEW TOP VIEW END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) NOTE SYMBOL 1.70 2.16 0.05 0.25 0.35 0.48 0.15 0.35 5.13 5.35 5.18 5.40 2, 3 7.70 8.26 0.51 0.85 SIDE VIEW SIDE VIEW θ...

  • Page 82: Datasheet Revision History

    Datasheet revision history Rev H - 09/07 1. Updated “Ordering Information” on page 78. Rev G - 06/07 1. “Not recommended for new design” Rev F - 06/05 1. Updated V in Table 4 on page 14 2. Added “Unconnected Pins” on page 51. 3.
  • Page 83 ATtiny15L Table of Contents Features....................1 Pin Configuration.................. 1 Description .................... 2 Block Diagram ...................... 3 Pin Descriptions....................4 Internal Oscillators ....................4 ATtiny15L Architectural Overview ............5 The General Purpose Register File ..............6 The ALU – Arithmetic Logic Unit................6 The Flash Program Memory .................
  • Page 84 I/O Port B ..................... 51 Memory Programming................ 54 Program and Data Memory Lock Bits..............54 Fuse Bits......................54 Signature Bytes ....................54 Calibration Byte ....................55 Programming the Flash ..................55 High-voltage Serial Programming............... 55 High-voltage Serial Programming Algorithm............56 High-voltage Serial Programming Characteristics ..........
  • Page 85 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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