Avr Attiny25/45/85 Memories; In-System Re-Programmable Flash Program Memory - Atmel ATtiny25 Manual

4.8.1 Interrupt Response Time

5. AVR ATtiny25/45/85 Memories

5.1

In-System Re-programmable Flash Program Memory

7598H–AVR–07/09
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clock cycles the Program Vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
This section describes the different memories in the ATtiny25/45/85. The AVR architecture has
two main memory spaces, the Data memory and the Program memory space. In addition, the
ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are lin-
ear and regular.
The ATtiny25/45/85 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory
for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
1024/2048/4096 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85
Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program
memory locations. "Memory Programming" on page 134
data serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing" on page 11.
ATtiny25/45/85
contains a detailed description on Flash
"Instruction Execution Tim-
13