System Control And Reset; Resetting The Avr; Reset Sources - Atmel ATtiny25 Manual

7.7.5 Watchdog Timer
7.7.6 Port Pins

8. System Control and Reset

8.1

Resetting the AVR

8.2

Reset Sources

7598H–AVR–07/09
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to "Watchdog Timer" on page 41
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk ) and the ADC clock (clk
I/O
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V /2 on an input pin can cause significant current even in active mode. Digital
CC
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to
"Digital Input Disable Register 0 – DIDR0" on page 110
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
The ATtiny25/45/85 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (V ).
POT
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minimum pulse length.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage V
Reset threshold (V
BOT
for details on how to configure the Watchdog Timer.
ADC
"Digital Input Enable and Sleep Modes" on page 51
/2, the input buffer will use excessive power.
CC
Figure 8-1 shows the reset logic.
) and the Brown-out Detector is enabled.
ATtiny25/45/85
) are stopped, the input buffers of the device
for details.
Table 8-1 defines the electrical
"Clock Sources" on page
is below the Brown-out
CC
for details on
23.
35