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EEPROM Data Memory
The ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes
can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described on page 33, specifying the EEPROM Address Register, the EEPROM Data Register,
and the EEPROM Control Register.
For SPI data downloading, see "Memory Programming" on page 39 for a detailed description.
Memory Access and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal
clock division is used.
Figure 14 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 14. The Parallel Instruction Fetches and Instruction Executions
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 15 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register
operands is executed and the result is stored back to the destination register.
Figure 15. Single-cycle ALU Operation
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T1
T2
ATtiny10/11/12
T3
T4
T3
T4
13
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