R&S NRP18S Series User Manual page 138

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R&S NRP18S-xx
EVENt status register part
The EVENt part indicates whether an event has occurred since the last reading, it is
the "memory" of the condition part. It only indicates events passed on by the transition
filters. It is permanently updated by the instrument.
You can only read this part. Reading the register clears it. This part is often equated
with the entire register.
ENABle status register part
The ENABle part determines whether the associated EVENt bit contributes to the sum
bit (see below). Each bit of the EVENt part is "ANDed" with the associated ENABle bit
(symbol '&'). The results of all logical operations of this part are passed on to the sum
bit via an "OR" function (symbol '+').
ENABle bit = 0: The associated EVENt bit does not contribute to the sum bit.
ENABle bit = 1: If the associated EVENt bit is 1, the sum bit is set to 1 as well.
You can read and write as required. Its contents are not affected by reading.
Sum bit
The sum bit is obtained from the EVENt and ENABle part for each register. The result
is then entered into a bit of the CONDition part of the higher-order register.
The instrument automatically generates the sum bit for each register. Thus an event
can lead to a service request throughout all levels of the hierarchy.
10.3.3 Status Byte (STB) and Service Request Enable Register (SRE)
The status byte register is already defined in IEEE 488.2. It gives a rough overview of
the sensor status, collecting information from the lower-level registers. It is comparable
with the CONDition register of a SCPI defined register and is at the highest level of
the SCPI hierarchy. Its special feature is that bit 6 acts as the summary bit of all other
bits of the status byte register.
The status byte register is read by
register is associated with the status byte register. The function of the service request
enable register corresponds to that of the ENABle register of the SCPI registers. Each
bit of the status byte register is assigned a bit in the service request enable register.
Bit 6 of the service request enable register is ignored. If a bit is set in the service
request enable register and the associated bit in the status byte register changes from
0 to 1, a service request (SRQ) is generated on the IEC/IEEE bus. This service request
triggers an interrupt in the controller configured for this purpose, and can be further
processed by the controller.
Set and read the service request enable register using *SRE.
See
User Manual 1178.3686.02 ─ 05
Figure 10-1.
or a serial poll. The service request enable
*STB?
Remote Control Basics
Status Reporting System
138