Novametrix Medical Systems 515 Service Manual page 17

Service Manual: Model 515
Theory of Operation:Digital Board
pin 9 of 15.36 KHz. This 65.1iisec pulse drives ICG16 which sends each o
outputs high sequentially from Q0-Q9 with each input pulse, then continu
recycles. This results in each Q output of ICG 16 producing a positive g(
pulse of 65.1|isec every 651|isec.
The QO and Q5 outputs are inverted by ICG7 pins 2 and 4, these out
drive the red and infrared LEDs on the front end board (LEDl and LI
lines). The QO and Q5 lines are NANDed together with the Q1 output f
ICG14 and outputs appear at ICG6 pins 6 and 8. This results in a nega
pulse of 2L7psec which occurs in the middle of LEDl and LED2 signals.
Q3 and Q8 outputs of ICG 16 are ORed at ICG5 and the result is inverted
1CG7 pm 6, this signal drives the shorting FETs on the front end board (I
This signal turns the grounding FETs on the front end board on before e
LED drive signal. The Q3 output from ICG 17 is also ORed with the Q3 and
outputs of ICG 16 at ICG5, this is done so that the FZ line can be overrid
and held on for front end calibration purposes.
1.3.8 Front End Board Interface
The Electrically Erasable Programmable Read Only Memory (E^PROM
controlled through ICG17 and half of ICG20. The EESK (EEPROM Se
Clock), EECS (EEPROM Chip Select) and the EEDI (EEPROM Data
lines are programmed by ICG 17 and the EEDO (EEPROM Data Out) is r
at bit 0 of the data bus by ICG20. The SAl and SA2 lines are controlled
ICG 17, these lines demultiplex the red and infrared AC signals, and discha
the AC coupling capacitors (FILTIN line) on the front end board.
One half of ICG20 reads data from the front end board, it reads the El
ROM's data out line and the red and infrared status lines (STLEDl ;
STLED2). The other half is used as a static address bus to the front (
board, this is used to reduce noise generated by the CPU's address and d
busses on the front end board. It works in such a way that the DP0-DP7 ;
AP0-AP2 lines are always at a high impedance state and the PWR line is
ways at a logic high unless these lines are actually being used to transfer d
to or from the front end board. All of the front end peripherals are within the
dress range of A0-B1H as shown in the following table.
Addres.s I/O E WR RD E Name
Function
80-87
88
89
90-97
90-97
98-9F
98-9F
A0-A7
A0-A7
A0-A7
0 0
0 X
0 X
0 0
0 X
0 X
0 0
0 X
0 0
0 X
X
X
X
X
0
0
X
X
X
0
X
1
1
X
X
X
X
X
1
X
WRDSP Display Module Write Enable
AS RTC Address Strobe
DS RTC Data Strobe
sees Sound Generator Chip Select
Led Status/EEPROM 0/P (ICG20)
— 8 bit I/P port (ICG 18 enable)
— 8 bit latch (ICG 17 enable)
—- Clear INT0 interrupt
WRADC Start conversion ADC chl-8
RDADC Read ADC chl-8