Novametrix Medical Systems 515 Service Manual page 16

Theory of Operation:Digital Board #2283
Service Manual: Model
1.3.5 VFD Interface
Communication between the VFD (Vacuum Fluorescent Display) and
CPU occurs at J403, there are two control lines (WRDSP and PROBUS) al
with the CPU data bus D0-D7. The WRDSP line controls the programming
the display, when this line is low (1CG3 pin 6) the data on the data bus is i
by the display module. The PROBUS is then brought low by the display rr
ule while it processes the infomiation sent to it. This line is read by the C
via ICG 18 before any data is sent to the display, if the line is low no data
be sent, it will be checked until it is high which indicates data can be sent.
The LNEST line (Line Status) indicates whether the monitor is running
of the line supply or off of battery power. When this line is high the monitc
hooked up to the mains supply and a green LED on the front panel is illumi
ed. LNEST is also connected to A7 of ICG 18 so the CPU can read the st;
of this signal. The RESET line is brought to the display module to blank
display during power up.
1.3.6 Keypanel Interface
The keypanel interfaces with the CPU via connector J2. All of the keys
the front panel are momentary normally open switches which short to gro
upon depression (J2 pin 1). The inputs from the keypanel SW1-SW6 are I
high by resistor pack RPGl and feed ICG 18, with the exception of ON/(
key which goes directly to the power supply board to turn the unit on and off.
1.3.7 Front End Timing
All of the timing waveforms for the 2288 front end board are derived f
the logic circuitry on the 2283 digital board. The CPU clock line (CLK) is di'
ed in half by ICG 10 to produce a 2.304 MHz signal. The next stage divi
that signal by 50, this is done by ICG 13, ICG8 and the other half of ICC
The negative edge of the 2.304MHz signal increments ICG 13, when Ql,
Q6 are all high (occurs after 49 counts) pin 8 of ICG8 will go high. This si|
appears at the "D" input of ICG 10 pin 12 and is transferred to the RESET
on ICG 13 on the next positive going pulse of the 2.304 MHz signal (ICG 10
11). This will reset ICG13 causing the Ql, Q5, Q6 outputs to reset to "0",
output of ICG8 pin 8 will go low, and this low will be transferred to the REJ
pin of ICG 13 (on positive clock signal to ICG 10) enabling it to begin coun
again. The resulting output is 49 clock cycles + 1 clock cycle during reset wl
gives the required count of 50, the output frequency is therefore 46.08 KHz.
The 46.08 KHz signal drives ICG14 which is negative edge triggered. A
two pulses the Q2 output of ICG14 will go high, this will cause ICGll pin !
reset ICG 14 on the next positive edge, this sends the Q2 output low. The
set signal will be removed on the next positive edge and incrementing will j
ceed on the following negative edge, this results in a pulsed output at ICC