Novametrix Medical Systems 515 Service Manual page 15

Service Manual: Model 515 Theory of Operation:Digital Board #;
transition of the DS pin. The RAV pin of IC7 is connected to the WR pin ol
CPU, it is low during write cycles and high during read cycles.
The decoding for the AS and DS lines are handled through logic circ
The inverted E line (synchronous clock output) is ORed with the lOE (In
Output Enable) at ICG3 pins 1,2 to produce a signal which controls the tin
of the AS and DS signals. This output is NORed with the Y1 output of lO
and the A0 line at ICG4 pin 10 for the AS line and is active in the add
range 80H, 82H etc. (when A0 is low). The DA line is the NORed resul
the Y1 of ICG 15 and the inverted A0 line which appears at ICG4 pin 9, th
active in the address range 81H, 83H etc. (when A0 is high).
The timing is achieved through C5, C6, C7, R5, R6 and Y2 which fom
oscillator circuit. This provides the RTC with a clock signal from which a(
rate time can be continually kept. The RTC is powered by the VBD (bac
voltage) supply which keeps the correct time while the monitor is off. If
VBD is removed or fails the PS pin (pin22) senses this through R4, C4,
and the time will not be used since it is invalid.
1.3.4 Tone Generator Circuit
The tone generator circuitry is based on the SN76496 tone gener
(ICS). The volume and frequency output is programmed by sending coded <
to ICS's data inputs D7 - D0 through the CPU data bus. When the CE (C
Enable) and WE (Write Enable) pins are low data is read from the data
by ICS. This process takes longer than the standard CPU write cycle so
READY line from ICS is tied to the CPU's WAIT line. When ICS is reac
data the READY line is brought low, this will cause the CPU to pause in
current state and hold the data on the data bus. When the data has been i
the READY line will return high and the CPU will operate as normal. The
and WE pins are tied together and are active low, this signal SGCS (So
Generator Chip Select) is derived by GRing the CPU WR line and the Y2 (
put from ICG15 at ICG3 pins 8, 9, 10.
The 4.608 MHz clock signal is divided in half by ICG 10 pin 6 and is c
nected to the CLK input on the tone generator. This frequency is divided dc
by the tone generator to obtain the desired output frequency. To prevent
random noise from being generated on power up the output from ICG 10 is
hibited by the RESET line which is connected to ICGlO's C (clear) input. 3
will prevent clock signals to ICS for the duration of the reset signal.
The AUDGUT pin from ICS is decoupled by R7 and C8 to prevent osci
tions. The output is then AC coupled through C9 and fed into IC9 which is
watt audio amplifier. The output from IC9 pin 5 is AC coupled through two
pacitors* in parallel to J401 pin 19 which with J401 pin 20 is run to the spea
which is mounted on the unit's chassis.
*On rev 00 boards they are C12A and CUB, on rev 01 boards they are C13 and C14.