Novametrix Medical Systems 515 Service Manual page 14

Theory of Operation:Digital Board #2283
Service Manual: Model
pins 4, 5, 6 which drive the IC's OE (Output Enable) line during a CPU i
cycle. The CE (Chip Enable) line is tied to address line A17, this will en
the line (active low) in the address range of 0000H to 0EEFH. Provis
have been made to enable the use of a 27C101 (1Mb EPROM) by bringing
dress line A16 to the EPROM socket. This would have the address range f
00000H to IFFFFH.
The Random Access Memory (RAM) consists of two HM62256 (:
IC6), the OE (Output Enable) and WE (Write Enable) lines are commoi
both RAMs. The OE lines are tied together with the EPROM's and there
is activated in the same way. The WE lines are enabled by the ORed resul
the ME (Memory Enable) and WR (Write) lines of the CPU, this ensures
the ICs will be written to only at CPU memory write cycles. The address
coding for the CE (Chip Enable) lines is handled by logic circuitry. The
line is inverted by ICG2 pin 10 then ORed with the A15 line by ICGl pins !
10, then it is ORed with the inverted A15 line (ICG2 pin 8) by ICGl pins
12, 13. This produces the CSMl (Chip Select Memory 1) and CSM2 (Chip
lect Memory 2) lines, when A17 is high and A15 is low CSMl will be sel
ed, when both A17 and A15 are high CSM2 will be selected. The add
range for IC4 is
20000H
to
27FFFH,
for IC6 it is from
28000H
to
2FF1
The decoded CE lines (CSMl and CSM2) are then individually ORed with
other signal at ICS pins 8, 9, 10 and ICS pins 11, 12, 13. This signal is the
suit of ORing the PSUST (PSU STatus), which is low when power is on
high when the unit is off, and the RSTDSL line which is high on reset only (
pins 1, 2, 3). As ICS is powered from the VBD supply (derived from
Vback
supply) it ensures that the CSMl and CSM2 lines are inhibited f
activating the CE lines on IC4 and IC6 when the power is off and during n
This avoids data corruption in the RAMs.
1.3.3 Real Time Clock (RTC)
The Real Time Clock (RTC) is IC7 an HD146818 RTC chip, its CE ((
Enable) line is driven by ORing the PSUST, RSTDSL at ICS pins 1, 2, 3 '
the RTSO line at ICS pins 4, S, 6. The RTSO is a latched output from the C
the IRQ (Interrupt Request) pin 19 of IC7 is connected to the INT2 line of
CPU, this is a low priority interrupt source. The RES pin of IC7 is connecte
the RESOUT line to ensure that the RTC does not generate any interrupts
power up.
The RTC has an internal multiplexed address and a bi-directional data
which is controlled through the R/W (Read/Write), AS (Address Strobe),
DS (Data Strobe) pins. When
R/W,
CE, DS inputs are low the address
pearing on the data bus is latched on the negative transition of the AS pin.
ta is written to the device in the same way except the AS pin is held low
the data is latched on the negative transition of the DS pin. When reading (
the R/W pin is high and the data is read by the CPU just before the nega