Datascope Accutorr Plus Service Manual page 86

Digital Section
The digital section of the board performs two distinct functions: analog section control
and interface to communications ic's.
This section is based on a 63C09E microprocessor. The analog section is accessed by
writing data into the control registers. Address decoding for generating control register
strobes CTRL-REG0*, CTRL-REG1*, and CTRL-REG2* is done by an EPLD address
decoder. The same address decoder is also responsible for monitoring status lines COMP*
and SAT*. THE 63C09E can observe the status of these lines by reading RD0 from the
assigned memory location (See Table XIV).
A watchdog timer chip provides RST and RST* signals to initialize the processor, the
three EPLD's and the two communications ICs. This watchdog is activated by any of a
number of sources: 1) a dip in the +5 volt logic supply, 2) a reset from the Accutorr Plus
with SpO host processor board on HSTRST*, or 3) lack of a strobe from a software control
2
loop on DOG-STR*. A 68C681 UART interface the processor to the host processor board.
Processor and communications shared memory consists of both static ram and flash ram.
Figure 2-7
SpO
2
Block Diagram
2-24 Accutorr Plus Service Manual
Revised 12/20/00
Chapter 2 - Theory of Operation