Datascope Accutorr Plus Service Manual page 75

CMOS SRAM, U4, U5
This memory made up of two 512K x 8 SRAMs, U4, and U5. The memories are
non-volatile due to the circuitry of Micromanager U19, and the Primary Battery Backup
Voltage Regulator, consisting of Q7, and U17. The timing for the two SRAM's are the
same. The SRAM write condition will be looked at first.
CS_RAM* must be active low 90 ns min before WR* rising edge. CS_RAM* is active
40ns max from S2 rising edge. WR* rising edge occurs when S6 falling edge occurs.
With one wait state, as above for the flash memories, there will be 3.5 clock periods.
Therefore, CS_RAM* will be active 168.25ns, compared to requirement of 90ns min.
This will meet the write timing.
CS_RAM* to data valid is 55ns max for SRAM read. Data will be valid 162.5ns max
from CS_RAM* active low. Therefore, with 3.5 clock periods to S6 falling edge, data
will be valid 68.25ns before S6 falling edge. This will meet the setup to S6 falling edge
of 15ns min.
Battery Backup Circuit
U17 is a 4V regulator which must supply current during battery mode. It supports the
Real Time Clock, U28, Micromanager, U19, and the two SRAM's. The RTC will draw
1uA, Micromanager, 20uA, and the SRAM's, 200uA. Total current draw from U17 is
221uA max. U17 can supply 30mA @ Vin=6V. VBULK can supply 21mA max at the
minimal voltage of 9.77V. The current supplied by U17 will then be minimized to
21mA.
U17 maximum input voltage is 14V. The maximum voltage at VBULK is 17V. Therefore,
a resistor divider network of R11 and R12 is used in conjunction with Q7 to lower the
voltage at U17-2. The maximum voltage at the Q7 base is 10.42V. Minimum Vbe for
Q7 is 0.65V. Maximum Vin will be 9.77V, which is lower than 14V as discussed above.
Micromanager, U19
The micromanager is a DS1239. It performs four functions:
1. System power on/off capability.
2. Watchdog functions.
3. Create CMOS SRAM to Non-volatile memory.
4. Power monitoring of VCC.
The MC68302 specifies to be held in reset for 100ms min upon power up. The DS1239
can hold the reset line, active low for 25ms min. In order to hold the reset line down for
100ms min, then the addition of a capacitor to the PBRST* input is needed. The
minimum time for the PBRST* input to reach 2.0V, logic hi to turn on unit, with a
47uF capacitor is 142ms.
The watchdog is monitored on U19-11. The maximum strobe period is 100ms. Therefore,
in order for the device not to reset the system, U19-11 must be strobed 100ms max.
The DS1239 can supply 1mA through U19-2, VCC_BACK, during battery mode. The
SRAM's will draw 200uA max during battery mode.
Accutorr Plus Service Manual
Chapter 2 - Theory of Operation
2-13
Revised 12/20/00