4.3.7. Board Interrupt Configuration Register (BICFG)
The Board Interrupt Configuration Register holds a series of bits defining the interrupt routing.
Table 19: Board Interrupt Configuration Register (BICFG)
Address
Bit
7
Name
UICF
Access
R/W
Reset
1
Bitfield
7
UICF
6
CFICF
5
CEICF
4
CDICF
1 - 0
WICF
4.3.8. Status Register 2 (STAT2)
The Status Register 2 holds status information related to the rear I/O configuration.
Table 20: Status Register 2 (STAT2)
Address
Bit
7
Name
Reserved
Access
Reset
Bitfield
5 - 4
RCFG
www.kontron.com
6
5
CFICF
CEICF
R/W
R/W
0
0
Description
UART IRQ3 and IRQ4 interrupt configuration:
0 = IRQ3 and IRQ4 interrupt disabled
1 = IRQ3 and IRQ4 interrupt enabled
CPCI fail signal interrupt configuration (FAL signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
CPCI enumeration signal interrupt configuration (ENUM signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
CPCI derate signal interrupt configuration (DEG signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
Watchdog interrupt configuration:
00 = Disabled
01 = IRQ5
10 = Reserved
11 = Reserved
6
5
R
00
Description
Rear I/O configuration:
00 = Rear I/O disabled (CP3005-SA front I/O version)
01 = COMA, GPIO
10 = Reserved
0x286
4
3
CDICF
Reserved
R/W
0
0x287
4
3
RCFG
R
N/A*
CP3005-SA – Rev. 0.6 Preliminary
2
1
WICF
R
R/W
00
2
1
MEZC
R
N/A*
0
00
0
// 38