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The CP3005-SA has one Watchdog timer function with a programmable timeout ranging from 125 milliseconds to
4096 seconds. Failure to strobe the Watchdog timer within the programmed timeout delay results in a system reset
or an interrupt.
There are four possible modes of operation:
Timer mode
Reset mode
Interrupt mode
Dual-stage mode
After the initial CP3005-SA power-on, the Watchdog is not enabled. To operate the Watchdog, the mode and timeout
period required must first be set and then the Watchdog enabled. Once enabled, the Watchdog can only be disabled
or the mode changed by powering down and then up again. To prevent a Watchdog timeout, the Watchdog must be
retriggered before timing out. This is done by writing a '1' to the WTR bit. In the event a Watchdog timeout does occur,
the WTE bit is set to '1'. What happens after this depends on the mode selected. The four operational Watchdog timer
modes can be configured by the WMD[1:0] bits, and are described as follows:
Timer mode
In this mode the Watchdog is enabled using the required timeout period. Normally, the Watchdog is retriggered by
writing a '1' to the WTR bit. In the event a timeout occurs, the WTE bit is set to '1'. This bit can be polled by the
application and handled accordingly. Once a Watchdog timeout occurs, the Watchdog is deactivated (WEN bit gets
reset to '0'). To continue using the Watchdog, write a '1' to the WTE bit to reset it, and then restart the Watchdog using
WEN.
Reset mode
This mode is used to force a hard reset in the event of a Watchdog timeout. In addition, the WTE bit is not reset by the
hard reset, which makes it available, if necessary, to determine the status of the Watchdog prior to the reset.
Interrupt mode
This mode generates an interrupt if a Watchdog timeout occurs. Configure the Watchdog interrupt in the Board
Interrupt Configuration Register (0x286), otherwise no interrupt will be generated. The interrupt handling is a
function of the application. If required, the WTE bit can be used to determine if a Watchdog timeout has occurred.
Once a Watchdog timeout occurs, the Watchdog is deactivated (WEN bit gets reset to '0').
Dual-stage mode
This is a complex mode where in the event of a timeout two things occur:
an interrupt is generated, and
the Watchdog is retriggered automatically.
In the event a second timeout occurs immediately following the first timeout, a hard reset will be generated. If the
Watchdog is retriggered normally, operation continues. The interrupt generated at the first timeout is available to the
application to handle the first timeout if required. As with all of the other modes, the WTE bit is available for
application use. Configure the Watchdog interrupt in the Board Interrupt Configuration Register (0x286), otherwise no
interrupt will be generated.
4.3.13. Board ID Low-Byte Register (BIDL)
Table 25: Board ID Low-Byte Register (BIDL)
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Description
0011 = 1 s
1011 = 256 s
0100 = 2 s
1100 = 512 s
0101 = 4 s
1101 = 1024 s
0110 = 8 s
1110 = 2048 s
0111 = 16 s
1111 = 4096 s
CP3005-SA – Rev. 0.6 Preliminary
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