Technical Specification; Table 1: Cp3005-Sa Main Specifications - Kontron CP3005-SA User Manual

2.6. Technical Specification

Table 1: CP3005-SA Main Specifications

Form factor
Processor
Chipset
Onboard Controllers
Memory
Interfaces
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Features Specifications
3U, 4HP CompactPCI
(100 mm x 160 mm)
8HP with mezzanine
CPU & Graphics The CP3005-SA supports the following processors:
Controller
Xeon 6C/12T, 2.7 GHz, nn MB, 45W
Core i5, 4C/8T, 2.5 GHz, 45W
PCH Intel® QM370 Chipset for Core i5, CM246 for Xeon
VGA Interface Via eDP to VGA converter (CH7517)
Gigabit Ethernet 2x Ethernet Controller (Intel® i210 and i219LM)
Trusted Platform TPM 2.0 Infineon SLB9670 using SPI
Module WIBU CodeMeter ASIC 1504-03
Embedded Controller Altera MAX V 5M1270ZF256I5N (CPLD)
Dual UART EXAR XR16L2750
PCIe-to-PCI bridge CPCI: Pericom PI7C9X110
System Memory Up to 32 GB DDR4 SDRAM memory with ECC running at
2400 MT/s, 1.2V on two SODIMM sockets
BIOS Flash 2x 16 MB SPI boot flash chips for two separate uEFI BIOS
images
Customized EEPROM I²C EEPROM with 64 kbit
Config Memories for i210: 16 Mbit SPI Flash
Ethernet interfaces
CompactPCI 32-bit/66MHz PCI interface with dedicated PCIe-to-PCI
bridge
System controller operation
3.3V or 5V signaling levels (universal signaling support)
Hot Swap support: Passive mode hot swappable
(automatic detection when plugged into the respective
CompactPCI slot)
Standard Rear I/O The following interfaces are routed to the rear I/O
connector J2:
COM1 and COM2 (RS-232 signaling)
2x Gigabit Ethernet
2x SATA gen I (1.5 Gbit/s) CPCI RESET
4x GPIs and 4x GPOs (LVTTL signaling), multiplexed with
COM2
Rear I/O with 2x USB2.0
modules CP-RIO03- 1x VGA
04 or CP-RIO03-04S
Gigabit Ethernet Two 10 BASE-T/100 Base-TX/1000 Base-T Gigabit
Ethernet interfaces based on one Intel® I219LM and one
Intel® I210 Gigabit switchable to the front panel or the rear
I/O
USB Two type A USB 2.0 connectors on the front panel, two
USB 2.0 ports on the rear I/O module CP-RIO03-04
One combined USB2.0/USB3.0 port on the MMEXT05
module
CP3005-SA – Rev. 0.6 Preliminary
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