Kontron CP3005-SA User Manual page 91

Sub-Screen Function
PEG Port 0:1:1
PEG Port 0:1:2
PEG Port 0:6:0
PEG Port Feature
Configuration
Program PCIe ASPM after
OpROM
Program Static Phase1 Eq
Gen3 Root Port Preset
value for each lane
Gen3 Endpoint Preset value
for each lane
Gen3 Endpoint Hint value
for each lane
Gen3 RxCTLE Control
Always Attempt SW EQ
Number of Presets to test
Allow PERST# GPIO Usage
SW EQEnable VOC
Jitter Dwell Time
Jitter Error Target
VOC Dwell Time
VOC Error Target
Generate BDAT PEG Margin
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Description
PEG0 Slot Power Limit Value 75
PEG0 Slot Power Limit Scale [1.0x]
PEG0 Physical Slot Number 1
Enable Root Port [Auto]
Max Link Speed [Auto]
PEG1 Slot Power Limit Value 75
PEG1 Slot Power Limit Scale [1.0x]
PEG1 Physical Slot Number 2
Enable Root Port [Auto]
Max Link Speed [Auto]
PEG2 Slot Power Limit Value 75
PEG2Slot Power Limit Scale [1.0x]
PEG2 Physical Slot Number 3
Enable Root Port [Auto]
Max Link Speed [Auto]
PEG3 Slot Power Limit Value 75
PEG3 Slot Power Limit Scale [1.0x]
PEG3 Physical Slot Number 4
Detect Non-Compliance Device [Enabled/Disabled]
[Enabled/Disabled]
[Enabled/Disabled]
[Lane 0 ... Lane 15: 7]
[Lane 0 ... Lane 15: 7]
[Lane 0 ... Lane 15: 2]
Bundle0 ... Bundle7: 0, PEG11 ... PEG13 [Enabled/Disabled],
DMI [Enabled/Disabled]
[Enabled/Disabled]
[Auto]
[Enabled/Disabled]
[Auto]
3000
2
10000
2
[Enabled/Disabled]
CP3005-SA – Rev. 0.6 Preliminary
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