Character Lcd Interface Signals; Voltage Compatibility; Ucf Location Constraints - Xilinx Spartan-3A User Manual

Chapter 5: Character LCD Screen

Character LCD Interface Signals

Table 5-1
Table 5-1: Character LCD Interface

Voltage Compatibility

The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However,
the FPGA's output levels are recognized as valid Low or High logic levels by the LCD. The
LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by
the FPGA meet the 5V TTL voltage level requirements.
The 390Ω series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a write-
only peripheral and never read from the display.

UCF Location Constraints

Figure 5-2
assignment and the I/O standard used.
44
shows the interface character LCD interface signals.
Signal Name FPGA Pin
LCD_DB<7> Y15
LCD_DB<6> AB16
LCD_DB<5> Y16
LCD_DB<4> AA12
LCD_DB<3> AB12
LCD_DB<2> AB17
LCD_DB<1> AB18
LCD_DB<0> Y13
LCD_E AB4
LCD_RS Y14
LCD_RW W13
provides the UCF constraints for the Character LCD, including the I/O pin
www.xilinx.com
Function
Data bit DB7
Data bit DB6
Data bit DB5
Data bit DB4
Data bit DB3 When using the four-bit
interface, drive these signals
Data bit DB2
High.
Data bit DB1
Data bit DB0
Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
Register Select
0: Instruction register during write operations.
Busy Flash during read operations
1: Data for read or write operations
Read/Write Control
0: Write, LCD accepts data
1: Read, LCD presents data
Spartan-3A/3AN Starter Kit Board User Guide
R
UG334 (v1.0) May 28, 2007