Number Of Blocks Used For Motion Dedicated Plc Instruction - Mitsubishi Electric R16MTCPU Programming Manual

Number of blocks used for Motion dedicated PLC instruction

Number of blocks for Multiple CPU dedicated instruction transmission area
■Number of CPU dedicated instruction transmission area
The Multiple CPU dedicated instruction transmission area used by Motion dedicated PLC instructions is managed in blocks
with a minimum unit of 16 words. The number of blocks used by each CPU is shown in the table below.
Number of Multiple CPU modules
2
3
4
■Number of blocks used for Motion dedicated PLC instruction
Each Motion dedicated PLC instruction uses a certain number of blocks in the CPU dedicated instruction transmission area
until the "complete device" turns on by the PLC CPU after instruction execution. The number of blocks used by Motion
dedicated PLC instructions is shown in the table below.
Instructions
M(P).SFCS/D(P).SFCS
M(P).SVST/D(P).SVST
M(P).SVSTD/D(P).SVSTD
M(P).CHGA/D(P).CHGA
M(P).CHGAS/D(P).CHGAS
M(P).CHGV/D(P).CHGV
M(P).CHGVS/D(P).CHGVS
M(P).CHGT/D(P).CHGT
M(P).MCNST/D(P).MCNST
M(P).DDWR/D(P).DDWR
M(P).DDRD/D(P).DDRD
M(P).BITWR/D(P).BITWR
M(P).GINT/D(P).GINT
*1 Calculated by the calculation expression
j=Number of characters of the Axis No. specified by (S1)
n=Number of positioning data points specified by (S1+1)
m=Number of characters of the character string data specified by (D1)
inside =Round up after the decimal
*2 When the number of writing data is 11 words or less, number of blocks used is 2.
*3 When the number of reading data is 13 words or less, number of blocks used is 2.
■Operation example
Below is an example when 12 M(P).SVST instructions (8 characters) and 12 M(P).DDWR instructions (number of writing data:
12 words) are executed simultaneously.
The number of blocks used is as follows;
12 M(P).SVST instructions issued  2 blocks each used + 12 M(P).DDWR instructions issued  2 blocks each used
= 48 (Total blocks used)
2 MOTION DEDICATED PLC INSTRUCTION
84
2.3 Precautions
Number of CPU dedicated instruction transmission area for each target CPU
599 blocks
299 blocks
199 blocks
Number of blocks used
1
*1
1 + (1 + j / 2 ) / 16
*1
1 + (n + m / 2 + 1) / 16
2
2
2
2
2
*1
1 + n / 16
*2
3
*3
2
*1
1 + (1 + j / 2 ) / 16
1